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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.googlemail.com with ESMTPSA id z12sm1635541edc.80.2022.02.24.06.44.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Feb 2022 06:44:49 -0800 (PST) Message-ID: Date: Thu, 24 Feb 2022 15:44:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2] KVM: x86: Fix emulation in writing cr8 Content-Language: en-US To: Zhenzhong Duan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: seanjc@google.com, vkuznets@redhat.com, wanpengli@tencent.com References: <20220210094506.20181-1-zhenzhong.duan@intel.com> From: Paolo Bonzini In-Reply-To: <20220210094506.20181-1-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/10/22 10:45, Zhenzhong Duan wrote: > In emulation of writing to cr8, one of the lowest four bits in TPR[3:0] > is kept. > > According to Intel SDM 10.8.6.1(baremetal scenario): > "APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0"; > > and SDM 28.3(use TPR shadow): > "MOV to CR8. The instruction stores bits 3:0 of its source operand into > bits 7:4 of VTPR; the remainder of VTPR (bits 3:0 and bits 31:8) are > cleared."; > > and AMD's APM 16.6.4: > "Task Priority Sub-class (TPS)-Bits 3 : 0. The TPS field indicates the > current sub-priority to be used when arbitrating lowest-priority messages. > This field is written with zero when TPR is written using the architectural > CR8 register."; > > so in KVM emulated scenario, clear TPR[3:0] to make a consistent behavior > as in other scenarios. > > This doesn't impact evaluation and delivery of pending virtual interrupts > because processor does not use the processor-priority sub-class to > determine which interrupts to delivery and which to inhibit. > > Sub-class is used by hardware to arbitrate lowest priority interrupts, > but KVM just does a round-robin style delivery. > > Fixes: b93463aa59d6 ("KVM: Accelerated apic support") > Signed-off-by: Zhenzhong Duan > Reviewed-by: Sean Christopherson > --- > v2: Add Sean's comments and "Fixes:" to patch description > > arch/x86/kvm/lapic.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index d7e6fde82d25..306025db9959 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2242,10 +2242,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) > > void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) > { > - struct kvm_lapic *apic = vcpu->arch.apic; > - > - apic_set_tpr(apic, ((cr8 & 0x0f) << 4) > - | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); > + apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); > } > > u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) Queued, thanks. Paolo