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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id 9-20020a05651c008900b002a776dbc277sm6458331ljq.124.2023.05.03.23.54.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 May 2023 23:54:11 -0700 (PDT) Message-ID: Date: Thu, 4 May 2023 08:54:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH 4/6] arm64: dts: qcom: sm8450-hdk: Add QMP & DP to SuperSpeed graph Content-Language: en-US To: Neil Armstrong , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20230503-topic-sm8450-graphics-dp-next-v1-0-d1ee9397f2a6@linaro.org> <20230503-topic-sm8450-graphics-dp-next-v1-4-d1ee9397f2a6@linaro.org> From: Konrad Dybcio In-Reply-To: <20230503-topic-sm8450-graphics-dp-next-v1-4-d1ee9397f2a6@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3.05.2023 15:10, Neil Armstrong wrote: > With support for the QMP combo phy to react to USB Type-C switch events, > introduce it as the next hop for the SuperSpeed lanes of the Type-C > connector, and connect the output of the DisplayPort controller > to the QMP combo phy. > > This allows the TCPM to perform orientation switching of both USB and > DisplayPort signals. > > Signed-off-by: Neil Armstrong > --- same comments as p3 Konrad > arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 71 ++++++++++++++++++++++++++++++++- > 1 file changed, 69 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > index e931545a2cac..52a14ae0321b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts > @@ -114,9 +114,18 @@ port@1 { > reg = <1>; > > pmic_glink_ss_in: endpoint { > - remote-endpoint = <&usb_1_dwc3_ss>; > + remote-endpoint = <&usb_1_qmpphy_out>; > }; > }; > + > + port@2 { > + reg = <2>; > + > + pmic_glink_sbu: endpoint { > + remote-endpoint = <&fsa4480_sbu_mux>; > + }; > + }; > + > }; > }; > }; > @@ -494,6 +503,36 @@ lt9611_out: endpoint { > }; > }; > > +&i2c5 { > + status = "okay"; > + clock-frequency = <100000>; > + > + fsa4480@42 { > + compatible = "fcs,fsa4480"; > + reg = <0x42>; > + > + interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>; > + > + vcc-supply = <&vreg_bob>; > + mode-switch; > + orientation-switch; > + svid = /bits/ 16 <0xff01>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + fsa4480_sbu_mux: endpoint { > + remote-endpoint = <&pmic_glink_sbu>; > + }; > + }; > + }; > + }; > +}; > + > &mdss { > status = "okay"; > }; > @@ -513,6 +552,20 @@ &mdss_dsi0_phy { > status = "okay"; > }; > > +&mdss_dp0 { > + status = "okay"; > + > + ports { > + port@1 { > + reg = <1>; > + mdss_dp0_out: endpoint { > + data-lanes = <0 1>; > + remote-endpoint = <&usb_1_qmpphy_dp_in>; > + }; > + }; > + }; > +}; > + > &mdss_mdp { > status = "okay"; > }; > @@ -766,7 +819,7 @@ &usb_1_dwc3_hs { > }; > > &usb_1_dwc3_ss { > - remote-endpoint = <&pmic_glink_ss_in>; > + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; > }; > > &usb_1_hsphy { > @@ -782,6 +835,20 @@ &usb_1_qmpphy { > > vdda-phy-supply = <&vreg_l6b_1p2>; > vdda-pll-supply = <&vreg_l1b_0p91>; > + > + orientation-switch; > +}; > + > +&usb_1_qmpphy_out { > + remote-endpoint = <&pmic_glink_ss_in>; > +}; > + > +&usb_1_qmpphy_usb_ss_in { > + remote-endpoint = <&usb_1_dwc3_ss>; > +}; > + > +&usb_1_qmpphy_dp_in { > + remote-endpoint = <&mdss_dp0_out>; > }; > > &vamacro { >