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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF000044A9.mail.protection.outlook.com (10.167.243.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.5 via Frontend Transport; Wed, 29 Jul 2026 08:18:19 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 29 Jul 2026 03:18:18 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 29 Jul 2026 01:18:18 -0700 Received: from [10.136.36.1] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Wed, 29 Jul 2026 03:18:15 -0500 Message-ID: Date: Wed, 29 Jul 2026 13:48:14 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] sched/fair: Prefer fully idle cores for NOHZ balancing To: Andrea Righi , Ingo Molnar , "Peter Zijlstra" , Juri Lelli , "Vincent Guittot" CC: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Christian Loehle , Shrikanth Hegde , "Phil Auld" , References: <20260728214442.1648483-1-arighi@nvidia.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <20260728214442.1648483-1-arighi@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Cd7E7CYjGJA6GV/kMRWAJwoNbWlEwaAyJkoapKtL5XS8uQOczSQuxqmSRhAJv7/mzZwAIq95Zhn3uQ3jgF5MdjruzCf0OWy0MNH59xzY9vGeI/EjmQmTsIgtyBi1U9LYN1JCcN8OaFrPzYIBHHT9pJEjS4mFFh9deCI1jiaEwDrcb4NSAMxH38O6idIm+oB2tJAd/juGoH+4asJEqCUGFE+CAWgBQ1D6w0wzIMa/983+h6QMnI1j4AMftevQAOwwcEoZ6862RALjDko/ju3050zQaouWtD6ChgBQ/bx28l1t8YJ/SA4/iK5yTY7KXPux1vq2sFfmpWnmg6lnsig6GXHyNmZdcxiIz+WtdScZzGUuPrjmPNA7x7At1yrL1nWBLStCCdrNtTuK04sJF8qABj4K4yYnKaYrNx9I3vc9oR5jdid7YRdWK+rOntEhdmxr X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2026 08:18:19.0116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e13289f8-d89e-4018-ff17-08deed49f2b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8759 Hello Andrea, On 7/29/2026 3:14 AM, Andrea Righi wrote: > @@ -13974,19 +13974,32 @@ static inline int find_new_ilb(void) > if (ilb_cpu == this_cpu) > continue; > > - if (idle_cpu(ilb_cpu)) > + if (!idle_cpu(ilb_cpu)) > + continue; > + > + /* > + * Running the idle load balancer on an idle sibling of a busy > + * SMT core can reduce the capacity available to its sibling. Prefer > + * a CPU whose entire core is idle, but retain the first idle CPU as > + * a fallback so idle balancing can still make progress when no fully > + * idle core exists. > + */ > + if (!sched_smt_active() || is_core_idle(ilb_cpu)) nit. is_core_idle() here would iterate all siblings and on systems with SMT-4 and SMT-8, that overhead is apparently visible when one thread per core is occupied based on past optimizations like f8858d96061f ("sched/fair: Optimize should_we_balance() for large SMT systems"). Copying the same approach from that optimization, can we do: (Only build tested) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index d78467ec6ee1..814bce21ccf1 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -13849,21 +13849,35 @@ static inline int on_null_domain(struct rq *rq) */ static inline int find_new_ilb(void) { + struct cpumask *ilb_cpus = this_cpu_cpumask_var_ptr(select_rq_mask); int this_cpu = smp_processor_id(); - const struct cpumask *hk_mask; - int ilb_cpu; + int ilb_cpu, fallback = -1; - hk_mask = housekeeping_cpumask(HK_TYPE_KERNEL_NOISE); + cpumask_and(ilb_cpus, nohz.idle_cpus_mask, housekeeping_cpumask(HK_TYPE_KERNEL_NOISE)); - for_each_cpu_and(ilb_cpu, nohz.idle_cpus_mask, hk_mask) { + for_each_cpu(ilb_cpu, ilb_cpus) { if (ilb_cpu == this_cpu) continue; - if (idle_cpu(ilb_cpu)) - return ilb_cpu; + if (!idle_cpu(ilb_cpu)) + continue; + + if (sched_smt_active() && !is_core_idle(ilb_cpu)) { + if (fallback == -1) + fallback = ilb_cpu; + /* + * If the core is not idle, and first SMT sibling which is + * idle has been found, then its not needed to check other + * SMT siblings for idleness: + */ + cpumask_andnot(ilb_cpus, ilb_cpus, cpu_smt_mask(ilb_cpu)); + continue; + } + + return ilb_cpu; } - return -1; + return fallback; } /* --- It is safe to use "select_rq_mask" here since this is the tick handler trying to find an ilb_cpu and "select_rq_mask" is only used in contexts with IRQs disabled. It can probably be renamed to suggest that it is safe to be used in any IRQ disabled context as a temporary mask. Thoughts? -- Thanks and Regards, Prateek