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Thu, 22 Oct 2026 02:29:22 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c468a1eecbcsm87380366b.7.2026.10.22.02.29.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Oct 2026 02:29:22 -0700 (PDT) Message-ID: Date: Thu, 22 Oct 2026 11:29:18 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B To: sophon@radxa.com, Bjorn Helgaas , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Bartosz Golaszewski , Linus Walleij , Dmitry Baryshkov Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Stephen Chen , Junhao Xie , dragon@radxa.com, Daniele Briguglio References: <20261009-q8b-dts-v2-0-eda11e5dea8b@radxa.com> <20261009-q8b-dts-v2-4-eda11e5dea8b@radxa.com> <3bb9a390-3b5e-4321-a25f-77e4f5c88f9a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; 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[...] >>> +/* M-key Gen3 x4 */ >>> +&pcie2a { >>> +    /* Place ECAM and BAR space above 4 GiB to accommodate large BARs. */ >>> +    reg = <0x0 0x01c20000 0x0 0x3000>, >>> +          <0x0 0x3c000000 0x0 0xf1d>, >>> +          <0x0 0x3c000f20 0x0 0xa8>, >>> +          <0x0 0x3c001000 0x0 0x1000>, >>> +          <0x5 0x00000000 0x0 0x10000000>, /* ECAM config */ >>> +          <0x0 0x01c23000 0x0 0x1000>; >>> + >>> +    ranges = /* IO (1 MiB) */ >>> +         <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, >>> +         /* 32-bit non-prefetchable memory (256 MiB) */ >>> +         <0x02000000 0x0 0x40000000 0x5 0x10000000 0x0 0x10000000>, >>> +         /* 64-bit non-prefetchable memory (3.5 GiB) */ >>> +         <0x03000000 0x5 0x20000000 0x5 0x20000000 0x0 0xe0000000>; >> >> Please drop this change on the board side, this is SoC-specific. >> Likewise for the other ports. >> > > Ack. Do you think this change can be applied to SoC DTSI? Yes. I'm not sure about the extended ECAM thing because we seem to have never moved forward with enabling that (oversight?) but in general: PCIeN | base | sz | ----------------------------------------- pcie4 | 0x4_0000_0000 | 1024 MiB pcie3b | 0x4_4000_0000 | 1024 MiB pcie3a | 0x4_8000_0000 | 1024 MiB pcie2b | 0x4_c000_0000 | 1024 MiB pcie2a | 0x5_0000_0000 | 4096 MiB >>> +&sdc2 { >>> +    pinctrl-0 = <&sdc2_default_state>; >>> +    pinctrl-1 = <&sdc2_sleep_state>; >>> +    pinctrl-names = "default", "sleep"; >>> + >>> +    full-pwr-cycle; >> >> Hm, is that something that comes from the controller itself? Should >> we advertise it on other SoCs too? >> > > It is observed that the boot firmware can leave an inserted SD card in a state that makes the first Linux enumeration fall back to 50 MHz high-speed mode. This property allows the MMC core to fully cycle the controllable card supply after voltage selection so UHS-I voltage switching succeeds reliably. Got it, maybe let's add a comment Konrad