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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: C3CE021CA1 X-Spam-Level: X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com]; RCVD_TLS_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; DKIM_TRACE(0.00)[suse.de:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:dkim,suse.de:mid] X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Rspamd-Action: no action X-Spam-Score: -3.01 X-Spam-Flag: NO Hi Florian, On 10/14/24 20:07, Florian Fainelli wrote: > On 10/14/24 06:07, Stanimir Varbanov wrote: >> Use canned MDIO writes from Broadcom that switch the ref_clk output >> pair to run from the internal fractional PLL, and set the internal >> PLL to expect a 54MHz input reference clock. >> >> Without this RPi5 PCIe cannot enumerate endpoint devices on >> extension connector. > > You could say that the default reference clock for the PLL is 100MHz, > except for some devices, where it is 54MHz, like 2712d0. AFAIR, 2712c1 > might have been 100MHz as well, so whether we need to support that > revision of the chip or not might be TBD. I'm confused now, according to [1] : BCM2712C1 - 4GB and 8GB RPi5 models BCM2712D0 - 2GB RPi5 models My device is 4GB RPi5 model so I would expect it is BCM2712C1, thus according to your comment the PLL PHY adjustment is not needed. But I see that the PCIex1 RC cannot enumerate devices on ext PCI connector because of link training failure. Implementing PLL adjustment fixes the failure. ~Stan [1] https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712