From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D272DC355 for ; Thu, 27 Nov 2025 09:30:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764235834; cv=none; b=B/SodkdRnkpdwVlXCIzT9DvU6v3BuIYm71dDvlRjIWexPgqMwcDOjlKPlveuTEHX7/8U5wBU5vxSQBo30CCzq12DgQL9VCgc8lgvyQZw8psdlDp8prSmfoGaZQV9TVLc+WdWai1xBoCkekwrBA4XQyv779KXUuwVDoX5XSx2n2Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764235834; c=relaxed/simple; bh=nrqTGhMNLHDsWxwWQMBejKo/U6PrwHxvborlgHDgWxE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=JblbI+gOFeCmtDYbpLpzg+SLYoZFAd8jYL8Mi2tjzQPx+E5ZHzW/KlIld1Tfq+pBoHSg7agO4GB3n3zkYg5MPi9rU88umTLSut0X6Nu2ELxJRDxph9xosGMpKh5oY1Dtw1kL8QWUmQmC7Nxh1Q5KHlcrrqoVqDq+GU4W7LTDw+w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EEoXKIQG; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EEoXKIQG" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4775e891b5eso2297745e9.2 for ; Thu, 27 Nov 2025 01:30:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764235831; x=1764840631; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=LtTjB6Sx5erYKk3Ax2gxl821BwwmVPc6hYwHiojJ3es=; b=EEoXKIQGJlVplOBPfGhGyI0yLrQzzB5W21yjPlIXyaMRI3nOF6wAAXQCD12Ptjmwif vP3nuSc58MivQLccCWrW+M2UZ0h2wgZUqYV35zmS+nouT7pnOgweIcfpVEtQnNDZlNpM YB6Vk8ZO9fjlwKw2PBVfIqsmoxYQLvILQnaT9yfNpelimX7P+5bez/fJSwm7FjJf5tyS vkuGmSrk3wYwFHSTWEfvijum9JjIY0N6pXtPAszS/2q2n+2wJmb/Xd5qqtt7xKFy8+ty Qxo+WJu/52UGBdi5WUdI6Uve0RoARgBKrMT3xY0y6+KEV7HzvZv69miErgqDX1tvuATv gf+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764235831; x=1764840631; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LtTjB6Sx5erYKk3Ax2gxl821BwwmVPc6hYwHiojJ3es=; b=gBa0L6jBjnNSYNvdaiIqpWnYomXseUaD8n0/XGmDwvOJDFG3xnrOI2Mn5Z5f2RZ8Ho POdGgGc9pipeWMkMDnBvF3M3MMvSHP6bOX3tPO9mjUfCxdBOY3LWeaJCGE+iKm6YA54Q Wf7PtCyK+wLn1ffpK8B+KskIS1FHWjOYTVwsU9vQGy8lTPPk+A2jdv7KrADUGjvW8lzw d8wkIfhlhiC4gEvxVodcQUhefTaUG2pkuVhdylRf6HPt1LtW8cHlQobTIK9Fj7Rv210A T35kJm4I9Ur6GVaqv/FVjWmM+/C0xYgByu5zXBepSpobzs7l1NFnYiyzsycdpj9O6r5t 6W/Q== X-Forwarded-Encrypted: i=1; AJvYcCUzNWdQvbmTUrr5NxRXUYUGGB6k/iQ9OgLTYVZIo9/prXaF7zWQ0B6lr6adFuiIaZvgjnvxIblrTVE8/sc=@vger.kernel.org X-Gm-Message-State: AOJu0YydvCkymeE9ZS/+/ZIKJn2RyMWIRiMogksU5s4TS8Fv4ZjplT8O hyJVktrQU6oiA6xR0vxX1Ao4+ewlqjrL33BC+4QVooOuOX+b4ydvpIumQAPSpu2Xe88= X-Gm-Gg: ASbGncvx5Gg82LwQtd7275tOz9vYb/LX0N1ZkWzJJ43wMcgNl97yjxDgl3qpgCc9P3W M7w8AcMepSHugg2uC+mWqfAO1B3n9o/GRQKZGY6+k62PjY7xgpGcce9yFyJqIwDtUztLyOE1pgS ASyVzkbhJsRCRVUCxG+pL+9n7VCHNFTTZWq1dYVxYHchoyOAoeP0mRkQOaEk+lgpfEu/0arwXOd HT6lGQxm3nulHBLOxu7RvhHuuPVlDgW3fJwzBPZsCC8tANtWRGRQQGKgxYRsfQ/AGE3BlVuhgBf zNS3msaOMNhPMlSlw6yMLSbiKBlCv0C1nYNgvywmzFnNNNsKGrvNbDoCA5aQekBXWVTts7cnAht 5NawRnsL5RuJ4HYf4+XatsE4mjre+IHUn/PhzgWSNgVudCyPi1gf3lGzC8am7FKsCDiVwhnSSI9 OVyvVeh9I0HKx1Fv9f13b6tQdZhp8= X-Google-Smtp-Source: AGHT+IFcl0miy3Ysfcfm+o+Ga8ivsKmS01lnAk51q/lkIWAfpN1T1O+2M+fFwyIHwSA/yfDLAw2R6g== X-Received: by 2002:a05:600c:1994:b0:477:7af8:c88b with SMTP id 5b1f17b1804b1-477c01740e1mr217044285e9.11.1764235830914; Thu, 27 Nov 2025 01:30:30 -0800 (PST) Received: from [192.168.1.3] ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790b0cc186sm82555375e9.13.2025.11.27.01.30.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Nov 2025 01:30:30 -0800 (PST) Message-ID: Date: Thu, 27 Nov 2025 09:30:28 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] coresight: etm3x: Fix buffer overwrite in cntr_val_show() To: Leo Yan , Kuan-Wei Chiu Cc: Mike Leach , suzuki.poulose@arm.com, alexander.shishkin@linux.intel.com, pratikp@codeaurora.org, mathieu.poirier@linaro.org, gregkh@linuxfoundation.org, jserv@ccns.ncku.edu.tw, marscheng@google.com, ericchancf@google.com, milesjiang@google.com, nickpan@google.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251121002350.1166758-1-visitorckw@gmail.com> <172ca2d9-4a6f-4498-bdfd-8aa7428581ce@linaro.org> <05babb6d-a588-49f8-a34a-c82d5f58adf5@linaro.org> <68efd5a2-3b65-4f37-9bf0-40c4e5ade480@linaro.org> <20251127092231.GN724103@e132581.arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20251127092231.GN724103@e132581.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 27/11/2025 9:22 am, Leo Yan wrote: > On Thu, Nov 27, 2025 at 04:44:53PM +0800, Kuan-Wei Chiu wrote: > > [...] > >> I don't feel it is my place to say whether the etm3x driver should be >> removed entirely. > > Sorry for confusion. Your fix patch is welcome, this is useful no > matter if remove the ETMv3 driver or not. > >> However, if we decide to keep it, I agree that aligning cntr_val_show >> with the cntr_val_store behavior (using cntr_idx) makes more sense. >> >> Here is my plan for v2: >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >> index 762109307b86..77578885e8f3 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c >> @@ -717,26 +717,19 @@ static DEVICE_ATTR_RW(cntr_rld_event); >> static ssize_t cntr_val_show(struct device *dev, >> struct device_attribute *attr, char *buf) >> { >> - int i, ret = 0; >> u32 val; >> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> struct etm_config *config = &drvdata->config; >> >> if (!coresight_get_mode(drvdata->csdev)) { >> spin_lock(&drvdata->spinlock); >> - for (i = 0; i < drvdata->nr_cntr; i++) >> - ret += sprintf(buf, "counter %d: %x\n", >> - i, config->cntr_val[i]); >> + val = config->cntr_val[config->cntr_idx]; >> spin_unlock(&drvdata->spinlock); >> - return ret; >> - } >> - >> - for (i = 0; i < drvdata->nr_cntr; i++) { >> - val = etm_readl(drvdata, ETMCNTVRn(i)); >> - ret += sprintf(buf, "counter %d: %x\n", i, val); >> + return sprintf(buf, "%x\n", val); >> } >> >> - return ret; >> + val = etm_readl(drvdata, ETMCNTVRn(config->cntr_idx)); > > It is not right to read register at here (it cannot promise to read the > CPU (cp14) register on the target CPU). > > Please refer to the same function in coresight-etm4x-sysfs.c. I think > we can do the same thing at here. > That's a different fix than the display bug though. This change doesn't change that if it's already wrong. The display fix should go in alone and then if there is an issue with not running things on the right CPU that should go in separately. >> + return sprintf(buf, "%x\n", val); >> } >> >> static ssize_t cntr_val_store(struct device *dev, >> >> >> Given the upcoming merge window, I plan to submit this v2 after -rc1 >> is released. >> >> Alternatively, if the consensus is to drop the driver, I am happy to >> submit a patch for that instead. > > Please continue this patch. Thanks a lot! > > Leo