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Fri, 30 Jun 2023 13:41:24 +0000 (GMT) Message-ID: Date: Fri, 30 Jun 2023 15:41:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v3 0/9] Introduce SMT level and add PowerPC support Content-Language: fr To: Sachin Sant Cc: linuxppc-dev , linux-arch@vger.kernel.org, dave.hansen@linux.intel.com, open list , Ingo Molnar , bp@alien8.de, npiggin@gmail.com, tglx@linutronix.de References: <20230629143149.79073-1-ldufour@linux.ibm.com> <58662E98-81B0-4553-9A75-4CA033720BE3@linux.ibm.com> From: Laurent Dufour In-Reply-To: <58662E98-81B0-4553-9A75-4CA033720BE3@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: kxEkzWPYxh7O2TCf2GQC8nQYJyPGRtgF X-Proofpoint-GUID: FY7QyRFyjNxYcWjk8u6p3xbJ6rrKhpXd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-30_05,2023-06-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306300116 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 30/06/2023 à 15:32, Sachin Sant a écrit : > > >> On 29-Jun-2023, at 8:01 PM, Laurent Dufour wrote: >> >> I'm taking over the series Michael sent previously [1] which is smartly >> reviewing the initial series I sent [2]. This series is addressing the >> comments sent by Thomas and me on the Michael's one. >> >> Here is a short introduction to the issue this series is addressing: >> >> When a new CPU is added, the kernel is activating all its threads. This >> leads to weird, but functional, result when adding CPU on a SMT 4 system >> for instance. >> >> Here the newly added CPU 1 has 8 threads while the other one has 4 threads >> active (system has been booted with the 'smt-enabled=4' kernel option): >> >> ltcden3-lp12:~ # ppc64_cpu --info >> Core 0: 0* 1* 2* 3* 4 5 6 7 >> Core 1: 8* 9* 10* 11* 12* 13* 14* 15* >> >> This mixed SMT level may confused end users and/or some applications. >> >> There is no SMT level recorded in the kernel (common code), neither in user >> space, as far as I know. Such a level is helpful when adding new CPU or >> when optimizing the energy efficiency (when reactivating CPUs). >> >> When SMP and HOTPLUG_SMT are defined, this series is adding a new SMT level >> (cpu_smt_num_threads) and few callbacks allowing the architecture code to >> fine control this value, setting a max and a "at boot" level, and >> controling whether a thread should be onlined or not. >> >> v3: >> Fix a build error in the patch 6/9 > > Successfully tested the V3 version on a Power10 LPAR. Add/remove of > processor core worked correctly, preserving the SMT level (on a kernel > booted with smt-enabled= parameter) > > Laurent (Thanks!) also provided a patch to update the ppc64_cpu & > lparstat utility. With patched ppc64_cpu utility verified that SMT level > changed at runtime was preserved across processor core add (on > a kernel booted without smt-enabled= parameter) > > Based on these test results > > Tested-by: Sachin Sant Thanks a lot, Sachin! Once this series is accepted, I'll send the series to update ppc64_cpu.