From: Florian Fainelli <f.fainelli@gmail.com>
To: Brian Masney <masneyb@kernel.org>, linux-mips@vger.kernel.org
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Paul Cercueil" <paul@crapouillou.net>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
hns@goldelico.com, paul@boddie.org.uk
Subject: Re: (subset) [PATCH v6 0/4] MIPS: CI20: Enable SMP with two CPUs
Date: Fri, 13 Nov 2026 13:52:40 -0800 [thread overview]
Message-ID: <bf28da39-23ae-4d17-af17-fe46177d8c80@gmail.com> (raw)
In-Reply-To: <179460306211.1364508.5876481329838567672.b4-ty@b4>
On 11/13/26 12:51, Brian Masney wrote:
>
> On Fri, 13 Nov 2026 11:08:32 -0800, Florian Fainelli wrote:
>> MIPS: CI20: Enable SMP with two CPUs
>>
>> This patch series resurrects SMP support for the CI20 board. This was
>> submitted back in 2020 by Zhou Yanjie.
>>
>> Changes in v6:
>>
>> [...]
>
> Applied, thanks!
>
> [1/4] clk: ingenic: Poll JZ4780 CPU1 power status atomically
> https://git.kernel.org/clk/linux/c/2c45b7e1e2f7
>
> Best regards,
Thanks Brian, I will remove that patch from future submissions.
--
Florian
prev parent reply other threads:[~2026-11-13 21:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 19:08 Florian Fainelli
2026-11-13 19:08 ` [PATCH v6 1/4] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-13 19:08 ` [PATCH v6 2/4] MIPS: Skip generic IPI setup for platform-specific callbacks Florian Fainelli
2026-11-13 19:08 ` [PATCH v6 3/4] MIPS: Ingenic: Add XBurst SMP support Florian Fainelli
2026-11-13 19:08 ` [PATCH v6 4/4] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-13 20:51 ` (subset) [PATCH v6 0/4] " Brian Masney
2026-11-13 21:52 ` Florian Fainelli [this message]
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