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Subject: Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available
To: James Hogan <jhogan@kernel.org>
Cc: Matt Redfearn <matt.redfearn@mips.com>, Ralf Baechle
 <ralf@linux-mips.org>, Thomas Gleixner <tglx@linutronix.de>,
 linux-mips@linux-mips.org, Jason Cooper <jason@lakedaemon.net>,
 Dengcheng Zhu <dengcheng.zhu@mips.com>, linux-kernel@vger.kernel.org,
 Philippe Ombredanne <pombredanne@nexb.com>,
 Paul Burton <paul.burton@mips.com>,
 Kate Stewart <kstewart@linuxfoundation.org>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com>
 <c9b5d20c-7adf-5308-1a45-21471d206d10@arm.com>
 <20180314154641.GA8976@saruman>
From: Marc Zyngier <marc.zyngier@arm.com>
Organization: ARM Ltd
Message-ID: <bf5ab15a-1151-1163-e139-a3657614d0fd@arm.com>
Date: Wed, 14 Mar 2018 15:53:45 +0000
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On 14/03/18 15:46, James Hogan wrote:
> On Wed, Mar 14, 2018 at 11:15:47AM +0000, Marc Zyngier wrote:
>> Hi Matt,
>> 
>> On 05/01/18 10:31, Matt Redfearn wrote:
>>> 
>>> This series enables the MIPS GIC driver to make use of the EIC
>>> mode supported in some MIPS cores. In this mode, the cores 6
>>> interrupt lines are switched to represent a vector number,
>>> 0..63. Currently all GIC interrupts are routed to a single CPU
>>> interrupt pin, but this is inefficient since we end up checking
>>> both local and shared interrupt flag registers for both local
>>> and shared interrupts. This introduces additional latency into
>>> the interrupt paths. With EIC mode this can be improved by
>>> using separate vectors for local and shared interrupts.
>>> 
>>> This series is based on 4.15-rc6 and has been tested on Boston,
>>> Malta & SEAD3 MIPS platforms implementing a GIC with and
>>> without EIC mode supported in hardware.
>> 
>> What the status of this series?
> 
> FYI I've been meaning to test it with KVM, since host EIC I think
> will affect KVM & guest stuff.

OK. I'll park that until I hear from you guys.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...