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From: Reinette Chatre <reinette.chatre@intel.com>
To: Juergen Gross <jgross@suse.com>, <linux-kernel@vger.kernel.org>,
	<x86@kernel.org>
Cc: Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>, Tony Luck <tony.luck@intel.com>,
	"Dave Martin" <Dave.Martin@arm.com>,
	James Morse <james.morse@arm.com>,
	Babu Moger <babu.moger@amd.com>
Subject: Re: [PATCH v3 1/5] x86/msr: Switch users of native_wrmsr() to native_wrmsrq()
Date: Mon, 26 Oct 2026 11:31:47 -0700	[thread overview]
Message-ID: <bf5e5341-f04e-4b34-afbe-55294d67d55c@intel.com> (raw)
In-Reply-To: <20261026141120.780172-2-jgross@suse.com>

Hi Juergen,

On 10/26/26 7:11 AM, Juergen Gross wrote:
> Switch all users of native_wrmsr() to native_wrmsrq() in order to
> prepare removal of native_wrmsr().
> 
> Signed-off-by: Juergen Gross <jgross@suse.com>
> ---
> V2:
> - switch order of hi and lo parts when oring them (Reinette Chatre)
> V3:
> - fix another lo | hi instance (Reinette Chatre)
> ---

No new comments since v1 
	https://lore.kernel.org/lkml/d6239cec-02dd-4b4e-bdd6-2bd6f88d8753@intel.com/

>  enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write);
> diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> index 0408ac7f66fd..24ded41652e3 100644
> --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> @@ -175,7 +175,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
>  	 * pseudo-locked followed by reading of kernel memory to load it
>  	 * into the cache.
>  	 */
> -	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid);
> +	native_wrmsrq(MSR_IA32_PQR_ASSOC, ((u64)plr->closid << 32) | rmid_p);

nit: The parentheses are unnecessary

>  
>  	/*
>  	 * Cache was flushed earlier. Now access kernel memory to read it
> @@ -212,7 +212,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
>  	 * Critical section end: restore closid with capacity bitmask that
>  	 * does not overlap with pseudo-locked region.
>  	 */
> -	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
> +	native_wrmsrq(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p);

This one looks good.

Thank you.

>  
>  	/* Re-enable the hardware prefetcher(s) */
>  	wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr);

While this change is fine I am curious why it has a different shape from
the other msr conversions you did that use the struct msr to compose the value?

Consider, for example:
	
	commit 4967c466ca38 ("x86/resctrl: Stop using 32-bit MSR interfaces")

I am curious especially since this cover letter note that this patch is based on the
series that the above merged commit is from.

Reinette

  reply	other threads:[~2026-10-26 18:31 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-26 14:11 [PATCH v3 0/5] x86/msr: Drop 32-bit interfaces of native MSR functions Juergen Gross
2026-10-26 14:11 ` [PATCH v3 1/5] x86/msr: Switch users of native_wrmsr() to native_wrmsrq() Juergen Gross
2026-10-26 18:31   ` Reinette Chatre [this message]
2026-10-27  7:11     ` Jürgen Groß
2026-10-26 14:11 ` [PATCH v3 2/5] x86/msr: Remove native_wrmsr() Juergen Gross
2026-10-26 14:11 ` [PATCH v3 3/5] x86/msr: Switch users of native_rdmsr() to native_rdmsrq() Juergen Gross
2026-10-26 14:11 ` [PATCH v3 4/5] x86/msr: Remove native_rdmsr() Juergen Gross
2026-10-26 14:11 ` [PATCH v3 5/5] x86/msr: Switch native_wrmsrq() from macro to inline function Juergen Gross

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