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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3494e84f446sm3060783a91.5.2025.12.04.17.01.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 17:01:44 -0800 (PST) Message-ID: Date: Fri, 5 Dec 2025 09:01:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jinlong Mao , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com> <20250908-enable-byte-cntr-for-tmc-v6-6-1db9e621441a@oss.qualcomm.com> <66d4488f-941a-4716-b81f-e0f9e1165931@arm.com> <5a0e4abf-9e7f-4ef9-af02-dd6e34f5cfa8@oss.qualcomm.com> <9c00516c-6e07-4c57-a1f1-6dfc32ab3a53@arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <9c00516c-6e07-4c57-a1f1-6dfc32ab3a53@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: NS1MjtiUupAZuLlJrd3kg4_G5-HMYcK2 X-Proofpoint-ORIG-GUID: NS1MjtiUupAZuLlJrd3kg4_G5-HMYcK2 X-Authority-Analysis: v=2.4 cv=esHSD4pX c=1 sm=1 tr=0 ts=69322efb cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=MQ8tZw8OEHbhgvfUyIkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDAwNiBTYWx0ZWRfXzrPYTnBZTAyc QCb4mKVHg1GwPP9nsgyi5yhqid194DTNpfAKt8FgXVRT02wmFCfNI5VMQ4Z1i2cjEvZ9nMHn1C3 SMpmGhy4ZyjOZEiPWktBx2YnGOF3PqD7W2U4x+7Vk89/pf/KZa4qggGpN8ZxdP67kyq9aPQscHp nKgsOhEHissROyVLJSjK1Di77rPK2/+K5YoznSmLVbbus7kT7A/Y6a2r+pJSrYgbSe1M72xPYin YIGxy7sswH1bWtyg3+Dnf8ZJCDQ1bzVWtAv75nO9idLhsvp2LYCqtawUAul9/CCvlW4/sra8fQW lEs9AjGsPTMrfzdN7NmlHaiHS/Vc7lsEJb4Je65URq3J8LKm+zJyrsuzxrWeuuguzmkRmrnrxmU l/1D+y32dic9P5vSv6adMYGQ8W3t2Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_06,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050006 On 12/4/2025 5:22 PM, Suzuki K Poulose wrote: > On 04/12/2025 02:53, Jie Gan wrote: >> >> >> On 12/4/2025 2:14 AM, Suzuki K Poulose wrote: >>> On 08/09/2025 03:01, Jie Gan wrote: >>>> Add an interrupt property to CTCU device. The interrupt will be >>>> triggered >>>> when the data size in the ETR buffer exceeds the threshold of the >>>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL >>>> register >>>> of CTCU device will enable the interrupt. >>>> >>>> Acked-by: Krzysztof Kozlowski >>>> Signed-off-by: Jie Gan >>>> --- >>>>   .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++ >>>> + + ++++++++++ >>>>   1 file changed, 17 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight- >>>> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight- >>>> ctcu.yaml >>>> index 843b52eaf872..ea05ad8f3dd3 100644 >>>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >>>> @@ -39,6 +39,16 @@ properties: >>>>       items: >>>>         - const: apb >>>> +  interrupts: >>>> +    items: >>>> +      - description: Byte cntr interrupt for etr0 >>>> +      - description: Byte cntr interrupt for etr1 >>>> + >>>> +  interrupt-names: >>>> +    items: >>>> +      - const: etr0 >>>> +      - const: etr1 >>> >> >> Hi Suzuki, >> >>> Why are they named "etr0" "etr1" ? That would be confusing, isn't it, >>> especially with the Linux driver naming things randomly for the TMC- >>> ETRs. >>> >> >> Yes, it will cause misunderstandings since the "etr0" here may not the >> right device we are expecting. >> >>> >>> What we want is the "port" number corresponding to the "TMC-ETR" being >>> monitored ? >>> >>> Have you explored other options, "port-0", "port-1" ? >>> >> >> I think it's much better. Will update in next version. > > I am not sure if there exists a better scheme for identifying or > numbering the interrupts. Happy to listen to the DT experts. > > Rob, Krzysztof, thoughts ? > Hi Suzuki, I was thinking how about the name "ETRIRQ0", "ETRIRQ1" etc... Thanks, Jie > Suzuki > > >> >> Thanks, >> Jie >> >>> Suzuki >>> >>>> + >>>>     in-ports: >>>>       $ref: /schemas/graph.yaml#/properties/ports >>>> @@ -56,6 +66,8 @@ additionalProperties: false >>>>   examples: >>>>     - | >>>> +    #include >>>> + >>>>       ctcu@1001000 { >>>>           compatible = "qcom,sa8775p-ctcu"; >>>>           reg = <0x1001000 0x1000>; >>>> @@ -63,6 +75,11 @@ examples: >>>>           clocks = <&aoss_qmp>; >>>>           clock-names = "apb"; >>>> +        interrupts = , >>>> +                     ; >>>> +        interrupt-names = "etr0", >>>> +                          "etr1"; >>>> + >>>>           in-ports { >>>>               #address-cells = <1>; >>>>               #size-cells = <0>; >>>> >>> >>> >> >