Re: [PATCH] perf vendor events arm64 AmpereOneX: Fix misspelled PublicDescription keys

[James Clark <james.clark@linaro.org>]

On 08/11/2026 18:38, TAKANO Mitsuhiro wrote:
> Sixteen of the 28 entries in mmu.json spell PublicDescription as
> "PublicDescrition"; the other 12 spell it correctly.  jevents.py reads
> only the keys it asks for by name, so those 16 fields are dead.

Shouldn't jevents enforce some kind of schema? This seems like a bug in 
the generator that it's allowed. And we have all the json files in one 
repo, so we can fix everything when adding strict validation.

> 
> Fixing them does not change the perf list output: every one of the 16
> entries has a BriefDescription with the same text, and jevents.py drops
> the long description when it equals the brief one (jevents.py:405).
> Running jevents.py for arm64 before and after this change gives a
> byte-identical generated string table.  This is a cleanup, not a fix for
> anything a user can see.
> 
> The file becomes self-consistent again, and the field works if the brief
> text is ever changed on its own.  No text, name, code or expression
> changes.
> 
> Written with Hermes Agent, an LLM assistant; the tables were regenerated
> with jevents.py on top of this change, perf was not rebuilt.
> 
> Signed-off-by: TAKANO Mitsuhiro <takano32@gmail.com>
> ---
>   .../arch/arm64/ampere/ampereonex/mmu.json     | 32 +++++++++----------
>   1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
> index 66d83b680651..9457f9be4ecc 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
> @@ -30,37 +30,37 @@
>           "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
> +        "PublicDescription": "Data TLB translation cache hit on S2L1 walk cache entry",
>           "EventCode": "0xd805",
>           "EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
>           "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
> +        "PublicDescription": "Data TLB translation cache hit on S2L0 walk cache entry",
>           "EventCode": "0xd806",
>           "EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
>           "BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Data-side S1 page walk cache lookup",
> +        "PublicDescription": "Data-side S1 page walk cache lookup",
>           "EventCode": "0xd807",
>           "EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
>           "BriefDescription": "Data-side S1 page walk cache lookup"
>       },
>       {
> -        "PublicDescrition": "Data-side S1 page walk cache refill",
> +        "PublicDescription": "Data-side S1 page walk cache refill",
>           "EventCode": "0xd808",
>           "EventName": "MMU_D_S1_WALK_CACHE_REFILL",
>           "BriefDescription": "Data-side S1 page walk cache refill"
>       },
>       {
> -        "PublicDescrition": "Data-side S2 page walk cache lookup",
> +        "PublicDescription": "Data-side S2 page walk cache lookup",
>           "EventCode": "0xd809",
>           "EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
>           "BriefDescription": "Data-side S2 page walk cache lookup"
>       },
>       {
> -        "PublicDescrition": "Data-side S2 page walk cache refill",
> +        "PublicDescription": "Data-side S2 page walk cache refill",
>           "EventCode": "0xd80a",
>           "EventName": "MMU_D_S2_WALK_CACHE_REFILL",
>           "BriefDescription": "Data-side S2 page walk cache refill"
> @@ -90,61 +90,61 @@
>           "BriefDescription": "Level 2 instruction translation buffer allocation"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry",
>           "EventCode": "0xd901",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry",
>           "EventCode": "0xd902",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry",
>           "EventCode": "0xd903",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry",
>           "EventCode": "0xd904",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry",
>           "EventCode": "0xd905",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
> +        "PublicDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry",
>           "EventCode": "0xd906",
>           "EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
>           "BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
>       },
>       {
> -        "PublicDescrition": "Instruction-side S1 page walk cache lookup",
> +        "PublicDescription": "Instruction-side S1 page walk cache lookup",
>           "EventCode": "0xd907",
>           "EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
>           "BriefDescription": "Instruction-side S1 page walk cache lookup"
>       },
>       {
> -        "PublicDescrition": "Instruction-side S1 page walk cache refill",
> +        "PublicDescription": "Instruction-side S1 page walk cache refill",
>           "EventCode": "0xd908",
>           "EventName": "MMU_I_S1_WALK_CACHE_REFILL",
>           "BriefDescription": "Instruction-side S1 page walk cache refill"
>       },
>       {
> -        "PublicDescrition": "Instruction-side S2 page walk cache lookup",
> +        "PublicDescription": "Instruction-side S2 page walk cache lookup",
>           "EventCode": "0xd909",
>           "EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
>           "BriefDescription": "Instruction-side S2 page walk cache lookup"
>       },
>       {
> -        "PublicDescrition": "Instruction-side S2 page walk cache refill",
> +        "PublicDescription": "Instruction-side S2 page walk cache refill",
>           "EventCode": "0xd90a",
>           "EventName": "MMU_I_S2_WALK_CACHE_REFILL",
>           "BriefDescription": "Instruction-side S2 page walk cache refill"
> 
> base-commit: fa4ad798f6f681031775266044ba1b0cf3c670bd