From: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
To: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>,
andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com,
quic_varada@quicinc.com, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
Date: Mon, 10 Mar 2025 15:30:24 +0530 [thread overview]
Message-ID: <bf79cf5a-0c50-49e0-b930-1ec5028e7d0c@oss.qualcomm.com> (raw)
In-Reply-To: <20250306112900.3319330-1-quic_mmanikan@quicinc.com>
On 3/6/2025 4:59 PM, Manikanta Mylavarapu wrote:
> The divider values in the sdcc1_apps frequency table were incorrectly
> updated, assuming the frequency of gpll2_out_main to be 1152MHz.
> However, the frequency of the gpll2_out_main clock is actually 576MHz
> (gpll2/2).
>
> Due to these incorrect divider values, the sdcc1_apps clock is running
> at half of the expected frequency.
>
> Fixing the frequency table of sdcc1_apps allows the sdcc1_apps clock to
> run according to the frequency plan.
>
> Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Kathiravan Thirumoorthy
<kathiravan.thirumoorthy@oss.qualcomm.com>
next prev parent reply other threads:[~2025-03-10 10:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-06 11:29 Manikanta Mylavarapu
2025-03-10 10:00 ` Kathiravan Thirumoorthy [this message]
2025-03-14 20:01 ` Bjorn Andersson
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