Re: [PATCH v5 rtw-next 5/7] wifi: rtw88: 8723b: add the RTL8723B chip driver

["Luka Gejak" <luka.gejak@linux.dev>]

September 30, 2026 at 20:03, "Bitterblue Smith" <rtl8821cerfe2@gmail.com mailto:rtl8821cerfe2@gmail.com?to=%22Bitterblue%20Smith%22%20%3Crtl8821cerfe2%40gmail.com%3E > wrote:


> 
> On 30/09/2026 12:16, Luka Gejak wrote:
> 
> > 
> > Add the Realtek RTL8723B 802.11n chip driver: the chip operations, the
> >  power sequences, the efuse layout, the RF and IQ calibration, and the
> >  chip specific coexistence handling.
> >  
[...]
> >  +/* The eight per-rate CCK transmit power registers are consecutive. */
> >  +#define REG_CCK_SWING 0x0a22
> > 
> This should be in reg.h.
> 

Will move it in v6.

> > 
> > +#define RTW_CCK_SWING_REG_NUM 8
> >  +
[...]
> >  + /* Enable Rx DMA timer masking: clear 0x0[2:0] and 0x2[15:0] only. */
> >  + val32 = rtw_read32(rtwdev, REG_SDIO_TX_CTRL);
> >  + val32 &= 0x0000fff8;
> >  + rtw_write32(rtwdev, REG_SDIO_TX_CTRL, val32);
> > 
> This is only for SDIO, it shouldn't run for PCI and USB.
> 

Understood, will add a check for SDIO.

> > 
[...]
> >  + rtw_dbg(rtwdev, RTW_DBG_RFK,
> >  + "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
> >  + rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
> > 
> This is misaligned.
> 
> > 
> > + rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
> >  + rtw_read32(rtwdev, REG_A_RXIQI),
> >  + rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
> >  + rtw_dbg(rtwdev, RTW_DBG_RFK,
> >  + "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
> >  + rtw_read32(rtwdev, REG_TXIQ_AB_S0),
> > 
> This too.
> 

My bad, and just one thing: checkpatch didn't catch these.
Will fix both either way.

Best regards,
Luka Gejak