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Thu, 28 May 2026 01:00:05 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 06/11] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Date: Thu, 28 May 2026 00:59:34 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4D:EE_|BY5PR12MB4050:EE_ X-MS-Office365-Filtering-Correlation-Id: ed03e4e6-fc6c-4743-aeaf-08debc8f311e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700016|82310400026|18002099003|22082099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: JXUjBViJlJQ96pdRbThMnR9kr4yBXltCL0InHCUyGVej08B8u5JWcy56z2IrNrXXnbYO8UYMOJqbpuBIQ0BDHyNbW6MYl+Q6TzSLDb8lyVbCSakClKt/w9yYSPJfgZB7PlGbWNsXL3R5svfVB9EyGVFQJ0K5+CXK9/x6BNzn2ylGk4rERcNedOWhJd/fl7gBaP1HhSHwKNDIfsFxDvks+3sxzcDBrEor9FF7vbTKW70X48Rs8YUyjybbFNzsCEcp3wU4HzNQaTIJaYVhcUZ7vYW7uxlPmlLHjKrQn76G10wzTnIMCfYrlDwey1JcVyPS23xDGsOFeTk/RMvoZg29OuQYdPObCg8GfYdFvjcrj1m0g4vgqJB3ElFxmCWFFObnMHl5XfRlvZAegbfa5gVu1i8B5XN11R8BkI4rYiNaUJEeDjPt6ELwS915ewV+BjuoH5OCve07MQhtUdNqRTySMPNPmiJUFfgOe7gblJdpLQj0XkC+UpXan+kuQN4Qr6atLmJSNYeBApexXp1vaNl4oP0QVV9QEjwHsgMQgE0s8VJAtbKxoVlg/8lDIg8plOIBEcyWQ17XgRVgOwvPDi2p9scsqOxKHFp2HxFmdk5MOB1obIVCCJf//62rb1F5y+iKWlQiW7BrSk1oRulsvY71gRcb5dnWMWuxaU8OPlRgYee4got5WRj2IQl0kFQvK/Iud1IseEQa/aa2TPeUOAdNJ0jqhZuHURVfMSJ6KBGeU4U= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700016)(82310400026)(18002099003)(22082099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6O9DagRcA/iN4QsPhwLuXtBcwoGY5ARN1EQDlErz3/+0KQJygFu3s7oe3FEtmkppcrhCRuN/no76ipdOIE5WMp5lvVWN/s0IPpW4IjEQwuOPp5SpbdDPSAWZJOn0GEbDg6z1epnqEZABtIvImwHjoiuWO2NbZ3+JFN3MZnrTxq6TpDHZeHh94VMnRs0zhUMIiRUIOHvrVf2RMjvZfhDOqLMjaeo+zotivftJMwvOgjSVHOdaZ+1Ko+wucclTNfBZ59Ia20jC1+7qFNKnbv+lOVfvI5VjUhKVI6eOEcrJ2NYxZ2LFkCm2Lvh+X+BalBQkVd01SJ+wEGysYWKfSVgmiD0iCX+c65vbBlCVmtSSymGdwfkgnFUxOUiQGS5405zRUPenDdlSug4WxUcPtydicZ47vJucOxdxi0cRZRhRZlXqQlKUsMCFq0KSaYg8lOUs X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 08:00:32.2022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed03e4e6-fc6c-4743-aeaf-08debc8f311e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4050 Now, arm_smmu_page_response() can issue CMDQ_OP_PRI_RESP for page requests from the IOPF infrastructure. Forward PRI requests from the priq into the IOPF infrastructure for PRI-enabled masters by building an iopf_fault from the priq entry and calling iommu_report_device_fault(). For an unrecognised StreamID or a master without master->pri_enabled, fall through to the existing "unexpected PRI request" log + LAST-page DENY path to release the credit per the PCIe PRI spec. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 061f1d46fda0d..371a8bbdf6756 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2242,6 +2242,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) { + struct arm_smmu_master *master; u32 sid, ssid; u16 grpid; bool ssv, last; @@ -2252,6 +2253,37 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) last = FIELD_GET(PRIQ_0_PRG_LAST, evt[0]); grpid = FIELD_GET(PRIQ_1_PRG_IDX, evt[1]); + mutex_lock(&smmu->streams_mutex); + master = arm_smmu_find_master(smmu, sid); + if (master && master->pri_enabled) { + struct iopf_fault iopf_fault = {0}; + struct iommu_fault *fault = &iopf_fault.fault; + + fault->type = IOMMU_FAULT_PAGE_REQ; + if (last) + fault->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (ssv) { + fault->prm.flags |= + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + fault->prm.pasid = ssid; + } + fault->prm.grpid = grpid; + if (evt[0] & PRIQ_0_PERM_READ) + fault->prm.perm |= IOMMU_FAULT_PERM_READ; + if (evt[0] & PRIQ_0_PERM_WRITE) + fault->prm.perm |= IOMMU_FAULT_PERM_WRITE; + if (evt[0] & PRIQ_0_PERM_EXEC) + fault->prm.perm |= IOMMU_FAULT_PERM_EXEC; + if (evt[0] & PRIQ_0_PERM_PRIV) + fault->prm.perm |= IOMMU_FAULT_PERM_PRIV; + fault->prm.addr = FIELD_GET(PRIQ_1_ADDR_MASK, evt[1]) << 12; + + iommu_report_device_fault(master->dev, &iopf_fault); + mutex_unlock(&smmu->streams_mutex); + return; + } + mutex_unlock(&smmu->streams_mutex); + dev_info(smmu->dev, "unexpected PRI request received:\n"); dev_info(smmu->dev, "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", -- 2.43.0