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([2a01:e0a:3d9:2080:6fea:600c:ca20:f54a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6e80fed75sm1215020f8f.66.2025.06.24.00.25.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jun 2025 00:25:46 -0700 (PDT) Message-ID: Date: Tue, 24 Jun 2025 09:25:45 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH v1 1/2] phy: mediatek: tphy: Clarify and add kerneldoc to mtk_phy_pdata To: AngeloGioacchino Del Regno , chunfeng.yun@mediatek.com Cc: vkoul@kernel.org, kishon@kernel.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com References: <20250623120315.109881-1-angelogioacchino.delregno@collabora.com> <20250623120315.109881-2-angelogioacchino.delregno@collabora.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250623120315.109881-2-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 23/06/2025 14:03, AngeloGioacchino Del Regno wrote: > As struct mtk_phy_pdata was almost fully documented, transfer > the comments into kerneldoc on top. > While at it, also rewrite the comments to both improve the writing > writing and the actual information in the documentation, and add a > description for the `version` member of the structure. > > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c > index 644a34bd2b0b..858824b4476e 100644 > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > @@ -277,19 +277,19 @@ enum mtk_phy_version { > MTK_PHY_V3, > }; > > +/** > + * mtk_phy_pdata - SoC specific platform data > + * @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only) > + * @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from > + * fractional mode to integer to output 26MHz for U2PHY > + * @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values > + * read from different nvmem (usually different eFuse array) > + * that is pointed at in the device tree node for this PHY > + * @version: PHY IP Version > + */ > struct mtk_phy_pdata { > - /* avoid RX sensitivity level degradation only for mt8173 */ > bool avoid_rx_sen_degradation; > - /* > - * workaround only for mt8195, HW fix it for others of V3, > - * u2phy should use integer mode instead of fractional mode of > - * 48M PLL, fix it by switching PLL to 26M from default 48M > - */ > bool sw_pll_48m_to_26m; > - /* > - * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse, > - * support sw way, also support it for v2/v3 optionally. > - */ > bool sw_efuse_supported; > enum mtk_phy_version version; > }; Reviewed-by: Neil Armstrong