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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id c6-20020a056870c08600b0014be94a12d0sm14722761oad.44.2023.01.16.07.27.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Jan 2023 07:27:08 -0800 (PST) Sender: Guenter Roeck Message-ID: Date: Mon, 16 Jan 2023 07:27:06 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v2 2/2] watchdog: mtk_wdt: Add reset_by_toprgu support Content-Language: en-US To: Allen-KH Cheng , Wim Van Sebroeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , linux-watchdog@vger.kernel.org Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org References: <20230116105305.31818-1-allen-kh.cheng@mediatek.com> <20230116105305.31818-3-allen-kh.cheng@mediatek.com> From: Guenter Roeck In-Reply-To: <20230116105305.31818-3-allen-kh.cheng@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/16/23 02:53, Allen-KH Cheng wrote: > In some cases, the MediaTek watchdog requires the toprgu to reset > timer after system resets. > > Provide a reset_by_toprgu parameter for configuration. > > Signed-off-by: Allen-KH Cheng Reviewed-by: Guenter Roeck > --- > drivers/watchdog/mtk_wdt.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index 3e6212591e69..a9c437598e7e 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -50,6 +50,7 @@ > #define WDT_MODE_IRQ_EN (1 << 3) > #define WDT_MODE_AUTO_START (1 << 4) > #define WDT_MODE_DUAL_EN (1 << 6) > +#define WDT_MODE_CNT_SEL (1 << 8) > #define WDT_MODE_KEY 0x22000000 > > #define WDT_SWRST 0x14 > @@ -70,6 +71,7 @@ struct mtk_wdt_dev { > spinlock_t lock; /* protects WDT_SWSYSRST reg */ > struct reset_controller_dev rcdev; > bool disable_wdt_extrst; > + bool reset_by_toprgu; > }; > > struct mtk_wdt_data { > @@ -279,6 +281,8 @@ static int mtk_wdt_start(struct watchdog_device *wdt_dev) > reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); > if (mtk_wdt->disable_wdt_extrst) > reg &= ~WDT_MODE_EXRST_EN; > + if (mtk_wdt->reset_by_toprgu) > + reg |= WDT_MODE_CNT_SEL; > reg |= (WDT_MODE_EN | WDT_MODE_KEY); > iowrite32(reg, wdt_base + WDT_MODE); > > @@ -408,6 +412,9 @@ static int mtk_wdt_probe(struct platform_device *pdev) > mtk_wdt->disable_wdt_extrst = > of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); > > + mtk_wdt->reset_by_toprgu = > + of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu"); > + > return 0; > } >