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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by DS1PEPF00017095.mail.protection.outlook.com (10.167.17.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Wed, 5 Aug 2026 08:59:45 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 5 Aug 2026 03:59:45 -0500 Received: from [10.136.47.95] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Wed, 5 Aug 2026 03:59:41 -0500 Message-ID: Date: Wed, 5 Aug 2026 14:29:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] sched/fair: Prefer fully idle cores for NOHZ balancing To: Andrea Righi , Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot CC: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Christian Loehle , Shrikanth Hegde , Phil Auld , Mete Durlu , References: <20260731191957.3199642-1-arighi@nvidia.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <20260731191957.3199642-1-arighi@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YU+kBeIArL4gB9U6Jj4TMcP3iH8VaT2r7DvaYaJAwg0WUM1oNwM0vvVCQWbdjrss9cdhvveEbcmdcMrfoo9l9ToQ9WhdWqX9BjS95CFFgyqjk74ds+A8D0MQbq6zxFB5W5ZQmbSk+rb1y6Y+HK2E0jdHXLLHpwDFRkh5/d22uaFKqu1diDn1Cm2L4Jd7fDfK/tHgyi30ry2rr9Ozgj6uBqK/wHK8wkNikbARYAbivZtLHPRPyQFg4rheHvC+jeO+4KDxByVGf17CrdDFRjyDwJvOwqPN9BSZu6zuzxpIRFYLmCzDB4wvPzCcW48SB5G+1j6UXlimvPrx2q2LJ440+qNiI3jxVnH+MsenQHCkS5WfeahXoTrQEd3NjRXpBS+aUyc8Gs6oxycrDzavHDqmshqeFawPm1L+2Zrjc0bSsm87+ePII2WWFLv+9MtY0Gcu X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2026 08:59:45.9249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1880988-7db2-4192-1aec-08def2cfe5c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017095.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7110 Hello Andrea, On 8/1/2026 12:49 AM, Andrea Righi wrote: > find_new_ilb() selects the first idle housekeeping CPU without > considering whether another thread is running on the same physical core. > On an SMT system, the idle load balancer can therefore activate both > siblings even when another housekeeping CPU has an entirely idle core. > > On most SMT systems, this is not problematic because the idle load > balancer is a short-lived activity and the transient wakeup of a sibling > has negligible performance impact. > > However, this can be particularly costly on NVIDIA Olympus cores used in > Vera. Briefly activating an otherwise idle sibling can reduce the > performance available to the other sibling and this effect does not > necessarily end once the activated sibling becomes idle: after the ILB > finishes and its CPU enters WFI, full single-thread performance is > restored only after the sibling has remained idle for a qualification > interval (10 Ki cycles on the tested Vera system). Repeated short > sibling wakeups can therefore sustain the interference even with little > actual overlap. > > Prevent this by preferring an idle housekeeping CPU whose entire SMT > core is idle. Retain the first idle CPU as a fallback when no fully idle > core is available, so NOHZ balancing continues to make forward progress. > Once a partially busy core has been examined, skip its remaining SMT > siblings to avoid repeating the core-idle check on wide SMT systems. > > Tests performed using an ad hoc GEMM benchmark running one CPU-intensive > task per SMT core within its CPU affinity mask improved from > approximately 6.2 TFLOP/s to 9.4 TFLOP/s. > > Note that this preference may wake a fully idle physical core instead of > using an idle sibling of an active core, potentially increasing ILB > wakeup latency or energy consumption on some architectures. It may also > scan additional CPUs before selecting the one to run the ILB. The > selection falls back to the first idle CPU when no fully idle SMT core > is available. Non-SMT systems continue to select the first idle > housekeeping CPU. I tested this on my end and couldn't really find a workload that shows a significant difference but I like the general idea of using an idle core for newidle balance so FWIW, feel free to include: Reviewed-by: K Prateek Nayak Tested-by: K Prateek Nayak [..snip..] > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c > index 37001c63452e5..574b6b3ee922a 100644 > --- a/kernel/sched/fair.c > +++ b/kernel/sched/fair.c > @@ -13965,28 +13965,66 @@ static inline int on_null_domain(struct rq *rq) > static inline int find_new_ilb(void) > { > int this_cpu = smp_processor_id(); > - const struct cpumask *hk_mask; > - int ilb_cpu; > + struct cpumask *ilb_cpus; > + int ilb_cpu, fallback = -1; nit. In case you are re-spinning this, could you rearrange these two line to follow reverse x-mas tree. -- Thanks and Regards, Prateek