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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e91cc0sm976035566b.26.2025.07.15.05.15.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 05:15:52 -0700 (PDT) Message-ID: Date: Tue, 15 Jul 2025 14:15:49 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/5] Introduce "non-pixel" sub node within iris video node To: Prakash Gupta , Bryan O'Donoghue , Dmitry Baryshkov Cc: Krzysztof Kozlowski , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <7b6db4fa-2f73-376d-4eb3-64c1c7e6cda3@quicinc.com> <5qsgbqml367yq6g5vb4lotrzulojqhi5zlwwribze373a63qrn@rxi4kwyt66m2> <4f38058d-a2f1-4ac5-b234-228cfb2e85ff@kernel.org> <1ad2ca1e-1d57-4ad8-a057-ab0d804f1d49@oss.qualcomm.com> <7da769b4-88e9-401f-bb21-0ff123818b9c@kernel.org> <6840d462-8269-4359-a6e5-d154842b62db@oss.qualcomm.com> <2hh3zkdwgqbdurpr4tibr3gjat6arwl3dd3gxakdaagafwjdrm@aj5em4tbsjen> <6c6f6bc9-7c34-4961-8b5e-e6d02c4b2f6d@linaro.org> <25c64712-960a-50b4-e7fa-398e4bf809ef@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <25c64712-960a-50b4-e7fa-398e4bf809ef@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDExMSBTYWx0ZWRfX4NimhTCJ4SK8 RWUByhqysVjoL7E+TYHURQK96wevdwdUsi3oScBd2M4L5j2K9ps0ECm8RbCwkG/NZVJp1eAUEVB KvraO4yFItcVuXHTdf3mlRXSo0xz9E0hgB6LbDXaB8uxvMds1HIGRbHOnYdczOAnZ25tJiNr6WV Ul+wRoBgup91glwcmNN6YlK2LLfHxguz0Sb/2Gb2NbPw2kL2CAfYJdAt+AomxRAzK0iMmQpMwa/ RDLdDDOslJW3ihO2J8uhWnUrTqiM9OK3SRJwwROdwBkegFv5FmALMz8OhJncNSGwXNd07CS63sh hzRaSbYExlrbc9Gl0tgOUyKzjCw8m5WKAKRd/o/BLxrVaKummJ0/JQ01LB393m1N9sCC1P8uNR8 3CylID8IvTS1T9jJPtfxfJDZhncde10RHY7kXOCGIWgwFqIUVcrqwOqaAuPhy1BvqXfOv2Or X-Proofpoint-GUID: zxOi-4dFaS_jgNn5oCu5rGCsSicu7Wvu X-Proofpoint-ORIG-GUID: zxOi-4dFaS_jgNn5oCu5rGCsSicu7Wvu X-Authority-Analysis: v=2.4 cv=Or9Pyz/t c=1 sm=1 tr=0 ts=6876467a cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=j_YMfRGaDDqHtg2ur-kA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-15_03,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507150111 On 7/10/25 8:18 PM, Prakash Gupta wrote: > > > On 7/5/2025 4:14 AM, Bryan O'Donoghue wrote: >> On 04/07/2025 17:45, Dmitry Baryshkov wrote: >>> What about instead: >>> >>> - keep IOMMU entries as is >> ack >> >>> - Add iommu-maps, mapping the non-pixel SID >>> - In future expand iommu-maps, describing the secure contexts? >> >> Interesting, we are _adding_ so that's not an ABI break and if I'm >> reading the documentation right, there's no hard rule on what iommu-map >> defines i.e. nothing to preclude us from encoding the information we >> want here. >> >> This might work. >> >> drivers/pci/controller/dwc/pcie-qcom.c::qcom_pcie_config_sid_1_9_0() >> >> You can register your platform device to the SID map you parse. > > I see few limitations with using iommu-map here, some of these are > listed in [1] > > 1. We can't specify SMR mask with iommu-map. > 2. We can't specify different iommu-addresses range for specific contexts. > 3. The secure CB support [2] would require vmid information associated > with per context. I think this can't be provided with iommu-map. FWIW iommu-map should probably be evolved to support passing more than one cell of iommu_spec in general.. For us specifically, it's only a matter of time before some platform's PCIe controller requires* we pass a non-zero SMR mask (unless we should be doing that already somewhere..) (* we can obviously do the masking manually and put the effective values in dt, but "eeh") Perhaps that can even be done without messing up backwards compatiblity (treat it as pseudocode, def incomplete): diff --git a/drivers/of/base.c b/drivers/of/base.c index 7043acd971a0..bca54035f90e 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2068,9 +2068,12 @@ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, struct device_node **target, u32 *id_out) { + const char *cells_prop_name __free(kfree); u32 map_mask, masked_id; + u32 cell_count; int map_len; const __be32 *map = NULL; + int ret; if (!np || !map_name || (!target && !id_out)) return -EINVAL; @@ -2084,7 +2087,15 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } - if (!map_len || map_len % (4 * sizeof(*map))) { + cells_prop_name = kasprintf(GFP_KERNEL, "#%s-cells", map_name); + if (!cells_prop_name) + return -EINVAL; + + ret = of_property_read_u32(np, cells_prop_name, &cell_count); + if (ret) + return ret; + + if (!map_len || map_len % ((2 + cell_count + 1) * sizeof(*map))) { pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_len); return -EINVAL; @@ -2106,7 +2117,7 @@ int of_map_id(const struct device_node *np, u32 id, u32 id_base = be32_to_cpup(map + 0); u32 phandle = be32_to_cpup(map + 1); u32 out_base = be32_to_cpup(map + 2); - u32 id_len = be32_to_cpup(map + 3); + u32 id_len = be32_to_cpup(map + cell_count - 1); if (id_base & ~map_mask) { pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", Konrad