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Thu, 16 Jul 2026 07:43:38 -0700 (PDT) Date: Thu, 16 Jul 2026 11:43:31 -0300 From: Leonardo Costa To: hongxing.zhu@oss.nxp.com Cc: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Zhu , leonardo.costa@toradex.com Subject: Re: [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY power and reference clock control Message-ID: References: <20260708035928.580236-1-hongxing.zhu@oss.nxp.com> <20260708035928.580236-2-hongxing.zhu@oss.nxp.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260708035928.580236-2-hongxing.zhu@oss.nxp.com> On Wed, Jul 08, 2026 at 11:59:27AM +0800, hongxing.zhu@oss.nxp.com wrote: > From: Richard Zhu > > Commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators") > introduced a boot hang on i.MX6Q/DL variants by changing the initialization > sequence. > > The issue stems from coupling PHY power (TEST_PD) and reference clock > (REF_CLK_EN) control in imx6q_pcie_enable_ref_clk(). When these are > managed together, the timing between PHY power-up and reference clock > enablement cannot be properly controlled, leading to initialization > failures. > > Fix this by separating the two concerns: > > - Move PHY power control (TEST_PD) to imx6q_pcie_core_reset() where it > logically belongs with reset operations. This ensures PHY power state > is managed as part of the core reset sequence. > > - Update imx6qp_pcie_core_reset() to call imx6q_pcie_core_reset() for > shared PHY power management, avoiding code duplication. > > - Make imx6q_pcie_enable_ref_clk() responsible only for reference clock > (REF_CLK_EN) control, simplifying its purpose. > > - Remove the 10us delay workaround from imx6q_pcie_enable_ref_clk() as > proper sequencing is now handled by the core_reset functions. > > This refactoring ensures PHY power is controlled during reset > operations, fixing the boot hang while improving code maintainability. > > Fixes: 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators") > Signed-off-by: Richard Zhu > --- Tested-by: Leonardo Costa