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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce38a000000b0063f88855ef2sm3377788qvl.101.2023.09.29.08.08.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Sep 2023 08:08:47 -0700 (PDT) Message-ID: Date: Fri, 29 Sep 2023 17:08:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 2/2] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Content-Language: en-US To: Miguel Luis , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev References: <20230925162057.27548-1-miguel.luis@oracle.com> <20230925162057.27548-3-miguel.luis@oracle.com> From: Eric Auger In-Reply-To: <20230925162057.27548-3-miguel.luis@oracle.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Miguel, On 9/25/23 18:20, Miguel Luis wrote: > Some _EL1 registers got included in the _EL2 ranges, which are not if they aren't too many, you may list them as it eases the review > affected by NV. Remove them, fine grain the ranges to exclusively > include the _EL2 ones and fold SPSR/ELR _EL2 registers into the > existing range. > > Signed-off-by: Miguel Luis Fixes: d0fc0a2519a6 (" KVM: arm64: nv: Add trap forwarding for HCR_EL2") ? > --- > arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++----- > 1 file changed, 38 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 9ced1bf0c2b7..f6d0c87803f4 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { > SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), > /* All _EL2 registers */ > SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), > - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), > + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV), > /* Skip the SP_EL1 encoding... */ > - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), > - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), > - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), > - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), I am not sure I fully understand the sysreg encoding but globally there are not so many _EL2 regs trapped with .NV. And I can see holes within somes ranges defined above (I searched all "if EL2Enabled() && HCR_EL2.NV == '1' then" in the ARM ARM). Maybe I don't know how to use the ARM ARM doc but I feel difficult to understand if the "holes" within the encoding of some ranges are unused or are allocated to some other sysregs, which wouldn't be trapped by /NV. I fear range encoding may be quite risky. > + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), > + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV), > + /* > + * Note that the spec. describes a group of MEC registers > + * whose access should not trap, therefore skip the following: > + * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, > + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, > + * VMECID_P_EL2. > + */ > SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), > - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), > + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV), > + /* ICH_AP0R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, > + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), > + /* ICH_AP1R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, > + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5), > + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV), > + /* ICH_LR_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_LR0_EL2, > + SYS_ICH_LR7_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_ICH_LR8_EL2, > + SYS_ICH_LR15_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1), > + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV), > + /* AMEVCNTVOFF0_EL2 */ > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 8, 0), > + sys_reg(3, 4, 13, 8, 7), CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 9, 0), > + sys_reg(3, 4, 13, 9, 7), CGT_HCR_NV), I think those 2 above ranges can be merged > + /* AMEVCNTVOFF1_EL2 */ > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 10, 0), > + sys_reg(3, 4, 13, 10, 7), CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 11, 0), > + sys_reg(3, 4, 13, 11, 7), CGT_HCR_NV), /* CNT*_EL2 */ > + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), > + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), > /* All _EL02, _EL12 registers */ > SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), > sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), not related to your patch but wrt the EL02 the only ones that I idenftied beeing trapped by NV using above search are CNTP_TVAL_EL02 3 5 14 2 0 CNTP_CTL_EL02 3 5 14 2 1 CNTP_CVAL_EL02 3 5 14 2 2 CNTV_TVAL_EL02 3 5 14 3 0 CNTV_CTL_EL02 3 5 14 3 1 CNTV_CVAL_EL02 3 5 14 3 2 Thanks Eric