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These registers are organized in H/W > as below on various SoCs. [...] > +struct pdc_desc { > + void __iomem *base; > + void __iomem *prev_base; > + u32 version; > + const struct pdc_regs *regs; > + const struct pdc_cfg *cfg; "cfg" is a bit vague, perhaps irq_cfg_fields or something similar? That said, "irq_cfg_fields" isn't very catchy, so if you have a better name, go ahead Konrad