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([2a01:e0a:106d:1080:544a:2852:f257:ebc5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49563eee22esm18488705e9.1.2026.07.20.05.39.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jul 2026 05:39:42 -0700 (PDT) Message-ID: Date: Mon, 20 Jul 2026 14:39:42 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH v2 2/3] drm/panel: ilitek-ili9805: Use dsi_multi in init To: Michail Tatas , michael@amarulasolutions.com, jesszhan0024@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260719190358.438699-1-michail.tatas@gmail.com> <20260719190358.438699-3-michail.tatas@gmail.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260719190358.438699-3-michail.tatas@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/19/26 21:03, Michail Tatas wrote: > Drop the struct ili9805_instr and the init table > and use init functions. > > Signed-off-by: Michail Tatas > --- > drivers/gpu/drm/panel/panel-ilitek-ili9805.c | 156 +++++++++---------- > 1 file changed, 73 insertions(+), 83 deletions(-) > > diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9805.c b/drivers/gpu/drm/panel/panel-ilitek-ili9805.c > index 7e9587afebbe..a70b9512746a 100644 > --- a/drivers/gpu/drm/panel/panel-ilitek-ili9805.c > +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9805.c > @@ -25,22 +25,9 @@ > #define ILI9805_SETEXTC_PARAMETER2 (0x98) > #define ILI9805_SETEXTC_PARAMETER3 (0x05) > > -#define ILI9805_INSTR(_delay, ...) { \ > - .delay = (_delay), \ > - .len = sizeof((u8[]) {__VA_ARGS__}), \ > - .data = (u8[]){__VA_ARGS__} \ > - } > - > -struct ili9805_instr { > - size_t len; > - const u8 *data; > - u32 delay; > -}; > - > struct ili9805_desc { > const char *name; > - const struct ili9805_instr *init; > - const size_t init_length; > + void (*init)(struct mipi_dsi_multi_context *ctx); > const struct drm_display_mode *mode; > u32 width_mm; > u32 height_mm; > @@ -56,65 +43,78 @@ struct ili9805 { > struct gpio_desc *reset_gpio; > }; > > -static const struct ili9805_instr gpm1780a0_init[] = { > - ILI9805_INSTR(100, ILI9805_EXTCMD_CMD_SET_ENABLE_REG, ILI9805_SETEXTC_PARAMETER1, > - ILI9805_SETEXTC_PARAMETER2, ILI9805_SETEXTC_PARAMETER3), > - ILI9805_INSTR(100, 0xFD, 0x0F, 0x10, 0x44, 0x00), > - ILI9805_INSTR(0, 0xf8, 0x18, 0x02, 0x02, 0x18, 0x02, 0x02, 0x30, 0x00, > - 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00), > - ILI9805_INSTR(0, 0xB8, 0x62), > - ILI9805_INSTR(0, 0xF1, 0x00), > - ILI9805_INSTR(0, 0xF2, 0x00, 0x58, 0x40), > - ILI9805_INSTR(0, 0xF3, 0x60, 0x83, 0x04), > - ILI9805_INSTR(0, 0xFC, 0x04, 0x0F, 0x01), > - ILI9805_INSTR(0, 0xEB, 0x08, 0x0F), > - ILI9805_INSTR(0, 0xe0, 0x00, 0x08, 0x0d, 0x0e, 0x0e, 0x0d, 0x0a, 0x08, 0x04, > - 0x08, 0x0d, 0x0f, 0x0b, 0x1c, 0x14, 0x0a), > - ILI9805_INSTR(0, 0xe1, 0x00, 0x08, 0x0d, 0x0e, 0x0e, 0x0d, 0x0a, 0x08, 0x04, > - 0x08, 0x0d, 0x0f, 0x0b, 0x1c, 0x14, 0x0a), > - ILI9805_INSTR(10, 0xc1, 0x13, 0x39, 0x19, 0x06), > - ILI9805_INSTR(10, 0xc7, 0xe5), > - ILI9805_INSTR(10, 0xB1, 0x00, 0x12, 0x14), > - ILI9805_INSTR(10, 0xB4, 0x02), > - ILI9805_INSTR(0, 0xBB, 0x14, 0x55), > - ILI9805_INSTR(0, MIPI_DCS_SET_ADDRESS_MODE, 0x08), > - ILI9805_INSTR(0, MIPI_DCS_SET_PIXEL_FORMAT, 0x77), > - ILI9805_INSTR(0, 0x20), > - ILI9805_INSTR(0, 0xB0, 0x01), > - ILI9805_INSTR(0, 0xB6, 0x31, 0x00, 0xef), > - ILI9805_INSTR(0, 0xDF, 0x23), > - ILI9805_INSTR(0, 0xB9, 0x02, 0x00), > -}; > +static void gpm1780a0_init(struct mipi_dsi_multi_context *ctx) > +{ > + mipi_dsi_dcs_write_seq_multi(ctx, ILI9805_EXTCMD_CMD_SET_ENABLE_REG, ILI9805_SETEXTC_PARAMETER1, > + ILI9805_SETEXTC_PARAMETER2, ILI9805_SETEXTC_PARAMETER3); > + mipi_dsi_msleep(ctx, 100); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xFD, 0x0F, 0x10, 0x44, 0x00); > + mipi_dsi_msleep(ctx, 100); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x18, 0x02, 0x02, 0x18, 0x02, 0x02, 0x30, 0x00, > + 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB8, 0x62); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xF1, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xF2, 0x00, 0x58, 0x40); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xF3, 0x60, 0x83, 0x04); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xFC, 0x04, 0x0F, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xEB, 0x08, 0x0F); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xe0, 0x00, 0x08, 0x0d, 0x0e, 0x0e, 0x0d, 0x0a, 0x08, 0x04, > + 0x08, 0x0d, 0x0f, 0x0b, 0x1c, 0x14, 0x0a); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x00, 0x08, 0x0d, 0x0e, 0x0e, 0x0d, 0x0a, 0x08, 0x04, > + 0x08, 0x0d, 0x0f, 0x0b, 0x1c, 0x14, 0x0a); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x13, 0x39, 0x19, 0x06); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0xe5); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB1, 0x00, 0x12, 0x14); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB4, 0x02); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xBB, 0x14, 0x55); > + mipi_dsi_dcs_write_seq_multi(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, MIPI_DCS_SET_PIXEL_FORMAT, 0x77); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x20); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB0, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB6, 0x31, 0x00, 0xef); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xDF, 0x23); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB9, 0x02, 0x00); > +} > > -static const struct ili9805_instr tm041xdhg01_init[] = { > - ILI9805_INSTR(100, ILI9805_EXTCMD_CMD_SET_ENABLE_REG, ILI9805_SETEXTC_PARAMETER1, > - ILI9805_SETEXTC_PARAMETER2, ILI9805_SETEXTC_PARAMETER3), > - ILI9805_INSTR(100, 0xFD, 0x0F, 0x13, 0x44, 0x00), > - ILI9805_INSTR(0, 0xf8, 0x18, 0x02, 0x02, 0x18, 0x02, 0x02, 0x30, 0x01, > - 0x01, 0x30, 0x01, 0x01, 0x30, 0x01, 0x01), > - ILI9805_INSTR(0, 0xB8, 0x74), > - ILI9805_INSTR(0, 0xF1, 0x00), > - ILI9805_INSTR(0, 0xF2, 0x00, 0x58, 0x40), > - ILI9805_INSTR(0, 0xFC, 0x04, 0x0F, 0x01), > - ILI9805_INSTR(0, 0xEB, 0x08, 0x0F), > - ILI9805_INSTR(0, 0xe0, 0x01, 0x0d, 0x15, 0x0e, 0x0f, 0x0f, 0x0b, 0x08, 0x04, > - 0x07, 0x0a, 0x0d, 0x0c, 0x15, 0x0f, 0x08), > - ILI9805_INSTR(0, 0xe1, 0x01, 0x0d, 0x15, 0x0e, 0x0f, 0x0f, 0x0b, 0x08, 0x04, > - 0x07, 0x0a, 0x0d, 0x0c, 0x15, 0x0f, 0x08), > - ILI9805_INSTR(10, 0xc1, 0x15, 0x03, 0x03, 0x31), > - ILI9805_INSTR(10, 0xB1, 0x00, 0x12, 0x14), > - ILI9805_INSTR(10, 0xB4, 0x02), > - ILI9805_INSTR(0, 0xBB, 0x14, 0x55), > - ILI9805_INSTR(0, MIPI_DCS_SET_ADDRESS_MODE, 0x0a), > - ILI9805_INSTR(0, MIPI_DCS_SET_PIXEL_FORMAT, 0x77), > - ILI9805_INSTR(0, 0x20), > - ILI9805_INSTR(0, 0xB0, 0x00), > - ILI9805_INSTR(0, 0xB6, 0x01), > - ILI9805_INSTR(0, 0xc2, 0x11), > - ILI9805_INSTR(0, 0x51, 0xFF), > - ILI9805_INSTR(0, 0x53, 0x24), > - ILI9805_INSTR(0, 0x55, 0x00), > -}; > +static void tm041xdhg01_init(struct mipi_dsi_multi_context *ctx) > +{ > + mipi_dsi_dcs_write_seq_multi(ctx, ILI9805_EXTCMD_CMD_SET_ENABLE_REG, ILI9805_SETEXTC_PARAMETER1, > + ILI9805_SETEXTC_PARAMETER2, ILI9805_SETEXTC_PARAMETER3); > + mipi_dsi_msleep(ctx, 100); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xFD, 0x0F, 0x13, 0x44, 0x00); > + mipi_dsi_msleep(ctx, 100); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x18, 0x02, 0x02, 0x18, 0x02, 0x02, 0x30, 0x01, > + 0x01, 0x30, 0x01, 0x01, 0x30, 0x01, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB8, 0x74); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xF1, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xF2, 0x00, 0x58, 0x40); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xFC, 0x04, 0x0F, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xEB, 0x08, 0x0F); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xe0, 0x01, 0x0d, 0x15, 0x0e, 0x0f, 0x0f, 0x0b, 0x08, 0x04, > + 0x07, 0x0a, 0x0d, 0x0c, 0x15, 0x0f, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x01, 0x0d, 0x15, 0x0e, 0x0f, 0x0f, 0x0b, 0x08, 0x04, > + 0x07, 0x0a, 0x0d, 0x0c, 0x15, 0x0f, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x15, 0x03, 0x03, 0x31); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB1, 0x00, 0x12, 0x14); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB4, 0x02); > + mipi_dsi_msleep(ctx, 10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xBB, 0x14, 0x55); > + mipi_dsi_dcs_write_seq_multi(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x0a); > + mipi_dsi_dcs_write_seq_multi(ctx, MIPI_DCS_SET_PIXEL_FORMAT, 0x77); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x20); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB0, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xB6, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x11); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xFF); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x24); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x00); > +} > > static inline struct ili9805 *panel_to_ili9805(struct drm_panel *panel) > { > @@ -160,16 +160,8 @@ static int ili9805_power_off(struct ili9805 *ctx) > static int ili9805_activate(struct ili9805 *ctx) > { > struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; > - int i; > > - for (i = 0; i < ctx->desc->init_length; i++) { > - const struct ili9805_instr *instr = &ctx->desc->init[i]; > - > - mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, instr->data, instr->len); > - > - if (instr->delay > 0) > - mipi_dsi_msleep(&dsi_ctx, instr->delay); > - } > + ctx->desc->init(&dsi_ctx); > > mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); > mipi_dsi_usleep_range(&dsi_ctx, 5000, 6000); > @@ -343,7 +335,6 @@ static void ili9805_dsi_remove(struct mipi_dsi_device *dsi) > > static const struct ili9805_desc gpm1780a0_desc = { > .init = gpm1780a0_init, > - .init_length = ARRAY_SIZE(gpm1780a0_init), > .mode = &gpm1780a0_timing, > .width_mm = 65, > .height_mm = 65, > @@ -351,7 +342,6 @@ static const struct ili9805_desc gpm1780a0_desc = { > > static const struct ili9805_desc tm041xdhg01_desc = { > .init = tm041xdhg01_init, > - .init_length = ARRAY_SIZE(tm041xdhg01_init), > .mode = &tm041xdhg01_timing, > .width_mm = 42, > .height_mm = 96, Reviewed-by: Neil Armstrong Thanks, Neil