On Wed, 30 Sep 2026, Ard Biesheuvel wrote: > From: Ard Biesheuvel > > (v2 never made it to linux-pci@ - please disregard it if you did get it) > > The non-prefetchable window of a PCI-to-PCI bridge can only decode > 32-bit addresses, and so even 64-bit non-prefetchable BARs of devices > below a bridge compete for the scarce MMIO space below 4 GB. > > The PCIe spec notes that marking such a BAR prefetchable still permits > correct operation as long as the entire path from the host to the device > is PCIe (PCIe r7.0, sec 7.5.1.2.1). The same applies when the OS places > a non-prefetchable BAR in a prefetchable bridge window, and so this > series permits that unless there is a bridge on the path to the root bus > that is not a PCIe Root Port or Switch Port, allowing 64-bit > non-prefetchable BARs to be placed above 4 GB. > > So add a new bus flag PCI_BUS_FLAGS_NO_NP_BARS_IN_P_WINDOWS, and wire it > up so that it is only set on buses where this relaxed placement is not > permitted. Then, use the flag to to decide whether to treat 64-bit NP > BARs as prefetchable only for the purpose of resource allocation (but > not for mapping the MMIO region or other reporting its properties) > > Patch #1 is a preparatory refactor of pci_bus_alloc_resource() with no > functional change, and patch #2 implements the relaxation. > > (based on v7.3-rc4) > > Cc: Bjorn Helgaas > Cc: "Ilpo Järvinen" > Cc: Lorenzo Pieralisi > Link: https://lore.kernel.org/linux-pci/20260910143440.3865663-2-ardb+git@google.com/ > > Ard Biesheuvel (2): > PCI: Add __pci_bus_alloc_resource() to allocate with explicit flags > PCI: Allow 64-bit non-prefetchable BARs in prefetchable windows > > drivers/pci/bus.c | 70 ++++++++++++++------ > drivers/pci/pci.c | 43 +++++++++++- > drivers/pci/pci.h | 7 ++ > drivers/pci/probe.c | 35 ++++++++++ > drivers/pci/setup-bus.c | 23 +++++-- > drivers/pci/setup-res.c | 30 ++++++--- > include/linux/pci.h | 1 + > 7 files changed, 169 insertions(+), 40 deletions(-) Hi, Nice. I gave this series a spin. Without pci=realloc, there weren't any changes in iomem (which is probably okay result). With pci=realloc, there seems to be some successful moves from 32-bit -> 64-bit but something goes wrong with it in some other cases. I looked into the simplest case with problems. VF BARs only vanished from 32-bit window, which I suppose is part of the correct behavior, but never reappeared on 64-bit side. Here's the timestampless diff for convenience: --- /dev/fd/63 2026-09-30 16:01:19.364780770 +0300 +++ /dev/fd/62 2026-09-30 16:01:19.364780770 +0300 @@ -72,21 +72,45 @@ pci 0000:d7:00.0: bridge window [mem 0xee800000-0xeebfffff]: releasing pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored -pci 0000:d7:00.0: bridge window [mem size 0x00000000] to [bus d8-d9] add_size 500000 add_align 100000 -pci 0000:d7:00.0: bridge window [mem 0xeed00000-0xef1fffff]: assigned -pci 0000:d8:00.0: ROM [mem 0xeed00000-0xeed7ffff pref]: assigned -pci 0000:d8:00.1: ROM [mem 0xeed80000-0xeedfffff pref]: assigned -pci 0000:d8:00.0: VF BAR 0 [mem 0xeee00000-0xeeefffff 64bit]: assigned -pci 0000:d8:00.0: VF BAR 3 [mem 0xeef00000-0xeeffffff 64bit]: assigned -pci 0000:d8:00.1: VF BAR 0 [mem 0xef000000-0xef0fffff 64bit]: assigned -pci 0000:d8:00.1: VF BAR 3 [mem 0xef100000-0xef1fffff 64bit]: assigned +pci 0000:d7:00.0: bridge window [mem size 0x00000000] to [bus d8-d9] add_size 100000 add_align 100000 +pci 0000:d7:00.0: bridge window [mem 0xee800000-0xee8fffff]: assigned +pci 0000:d8:00.0: ROM [mem 0xee800000-0xee87ffff pref]: assigned +pci 0000:d8:00.1: ROM [mem 0xee880000-0xee8fffff pref]: assigned +pci 0000:d8:00.0: VF BAR 0 [mem size 0x00100000 64bit]: can't assign; no space +pci 0000:d8:00.0: VF BAR 0 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.0: VF BAR 3 [mem size 0x00100000 64bit]: can't assign; no space +pci 0000:d8:00.0: VF BAR 3 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.1: VF BAR 0 [mem size 0x00100000 64bit]: can't assign; no space +pci 0000:d8:00.1: VF BAR 0 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.1: VF BAR 3 [mem size 0x00100000 64bit]: can't assign; no space +pci 0000:d8:00.1: VF BAR 3 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.0: ROM [mem 0xee800000-0xee87ffff pref]: releasing +pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.1: ROM [mem 0xee880000-0xee8fffff pref]: releasing +pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource restored +pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.1: ROM [mem 0xee800000-0xee87ffff pref]: assigned +pci 0000:d8:00.0: ROM [mem 0xee880000-0xee8fffff pref]: assigned +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resetting resource +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resetting resource +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resetting resource +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resetting resource pci 0000:d7:00.0: PCI bridge to [bus d8-d9] -pci 0000:d7:00.0: bridge window [mem 0xeed00000-0xef1fffff] +pci 0000:d7:00.0: bridge window [mem 0xee800000-0xee8fffff] pci 0000:d7:00.0: bridge window [mem 0x207fff400000-0x207fffcfffff 64bit pref] pci_bus 0000:d7: resource 4 [io 0xf000-0xffff window] pci_bus 0000:d7: resource 5 [mem 0xee800000-0xfbffffff window] pci_bus 0000:d7: resource 6 [mem 0x207000000000-0x207fffffffff window] -pci_bus 0000:d8: resource 1 [mem 0xeed00000-0xef1fffff] +pci_bus 0000:d8: resource 1 [mem 0xee800000-0xee8fffff] pci_bus 0000:d8: resource 2 [mem 0x207fff400000-0x207fffcfffff 64bit pref] pci 0000:d7:05.0: disabled boot interrupts on device [8086:2034] pci 0000:d8:00.0: CLS mismatch (128 != 32), using 64 bytes The problems could be related to pci=realloc not touching already assigned bridge windows in many cases. pbus_size_mem() has resource_assigned() check early so it won't size those bridge windows again. I've some unfinished patch to remove that restriction but have been busy solving the recent set of regressions. Because VF BARs are optional resources, their failures are considered acceptable so together with not trying to resize those windows, no failures are detected by the fitting algorithm. There are a few cases that are more messy than the one above. I'll try to later look if they are fine or not. Annoyingly VF BARs are left with the original base address when they fail, so they appear in lspci with what looks a valid address but the corresponding resource is not in the resource tree so it takes time to decipher if everything is properly assigned or not (when things move around in iomem diffing it won't easily tell it either). -- i.