From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67AC951EE04; Wed, 30 Sep 2026 18:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790793107; cv=none; b=qQ38BWVEt/MI29EcBkjgfegsHmSTy3lUQxT5uVEKl0SjTNkj+Os+6vm7JBFJ6zhh/thoHUEw10XpXqfC2wXsMLy5r+NPKicUSCHTJ90rDgtMycxRNlU9vJGzoz7jROP1xo2WH+1cg2q9Q0E9fOvwD5xBuOnRG50TtXfjXwUVFYU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790793107; c=relaxed/simple; bh=MJZyfxSrtbZYlFPd2aVippPfZhrOmDdWos9RBqjZEW4=; h=From:Date:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=Wq+VFYE3CcL5ATvlOIuGfPFQZR+4Q/dEzNS5wRxHVBhlqivIEiZEiGJI/AGc/Pc66Zr25BgsSHHwshkTqjhID2P2EHBuZyEorUwh+7beOaDJUUVyROBy0FQr536vSCezmdmlnQitPAzwpp5fp/tMxXinuOk8lfWJ5ybMecL6yTc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Zqx/6sfP; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Zqx/6sfP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1790793104; x=1822329104; h=from:date:to:cc:subject:in-reply-to:message-id: references:mime-version:content-id; bh=MJZyfxSrtbZYlFPd2aVippPfZhrOmDdWos9RBqjZEW4=; b=Zqx/6sfPFkN7ciAciPfRhtln67yUk9oOnEQMINz2ZSuCsIsKjJCaihUr /wfdV7SvIlma0B+uP9T5bE3rKYkGgoDyDfmCqo/hWwFuC3iJWHFvyW1R0 jm0Vq5AL8pEveleX99Dacw1Wg3pbwhdHJqXtFtbWm0IssswJsrKDdZekz nTfuWV+cQFdmQ9tf0yeiGw2swyRnmL9rOJJQkv1osRRCIBUihE/8JB/4B JF3oZe9713k8qSEMr0w4e4wFTYORV4SuReLDZyWD6YKaX2fUB2mZuR1Lu DkRWJ5BKNPA5yAxpwHEBXb2LveAxk/hw4xqfnEhkDeRy7LxJNcUxW+q1s g==; X-CSE-ConnectionGUID: OhfkAoPiTx6bFdh+xL//7w== X-CSE-MsgGUID: IT1BfaiVRAuUvYWh/9YDzg== X-IronPort-AV: E=McAfee;i="6800,10657,11921"; a="101703010" X-IronPort-AV: E=Sophos;i="6.27,133,1787036400"; d="pre'?post'?scan'208";a="101703010" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2026 11:31:43 -0700 X-CSE-ConnectionGUID: vwoXHK16RdCZ5KtqrCslvw== X-CSE-MsgGUID: qZp5VVnpTj28VJ844sA/CQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,133,1787036400"; d="pre'?post'?scan'208";a="275891632" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.106]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2026 11:31:40 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Wed, 30 Sep 2026 21:31:37 +0300 (EEST) To: Ard Biesheuvel cc: linux-pci@vger.kernel.org, LKML , Ard Biesheuvel , Bjorn Helgaas , Lorenzo Pieralisi Subject: Re: [PATCH v3 0/2] PCI: Allow non-prefetchable BARs in prefetchable windows In-Reply-To: <20260930103036.248989-4-ardb+git@google.com> Message-ID: References: <20260930103036.248989-4-ardb+git@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323328-683533231-1790792162=:1755" Content-ID: <35cd27f5-408c-6172-0e82-88871bda0c25@linux.intel.com> This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-683533231-1790792162=:1755 Content-Type: text/plain; CHARSET=ISO-8859-15 Content-Transfer-Encoding: QUOTED-PRINTABLE Content-ID: <48987c92-762b-2f01-2746-4cf1b9835cee@linux.intel.com> On Wed, 30 Sep 2026, Ard Biesheuvel wrote: > From: Ard Biesheuvel >=20 > (v2 never made it to linux-pci@ - please disregard it if you did get it) >=20 > The non-prefetchable window of a PCI-to-PCI bridge can only decode > 32-bit addresses, and so even 64-bit non-prefetchable BARs of devices > below a bridge compete for the scarce MMIO space below 4 GB. >=20 > The PCIe spec notes that marking such a BAR prefetchable still permits > correct operation as long as the entire path from the host to the device > is PCIe (PCIe r7.0, sec 7.5.1.2.1). The same applies when the OS places > a non-prefetchable BAR in a prefetchable bridge window, and so this > series permits that unless there is a bridge on the path to the root bus > that is not a PCIe Root Port or Switch Port, allowing 64-bit > non-prefetchable BARs to be placed above 4 GB. >=20 > So add a new bus flag PCI_BUS_FLAGS_NO_NP_BARS_IN_P_WINDOWS, and wire it > up so that it is only set on buses where this relaxed placement is not > permitted. Then, use the flag to to decide whether to treat 64-bit NP > BARs as prefetchable only for the purpose of resource allocation (but > not for mapping the MMIO region or other reporting its properties) >=20 > Patch #1 is a preparatory refactor of pci_bus_alloc_resource() with no > functional change, and patch #2 implements the relaxation. >=20 > (based on v7.3-rc4) >=20 > Cc: Bjorn Helgaas > Cc: "Ilpo J=E4rvinen" > Cc: Lorenzo Pieralisi > Link: https://lore.kernel.org/linux-pci/20260910143440.3865663-2-ardb+git= @google.com/ >=20 > Ard Biesheuvel (2): > PCI: Add __pci_bus_alloc_resource() to allocate with explicit flags > PCI: Allow 64-bit non-prefetchable BARs in prefetchable windows >=20 > drivers/pci/bus.c | 70 ++++++++++++++------ > drivers/pci/pci.c | 43 +++++++++++- > drivers/pci/pci.h | 7 ++ > drivers/pci/probe.c | 35 ++++++++++ > drivers/pci/setup-bus.c | 23 +++++-- > drivers/pci/setup-res.c | 30 ++++++--- > include/linux/pci.h | 1 + > 7 files changed, 169 insertions(+), 40 deletions(-) Hi, Nice. I gave this series a spin. Without pci=3Drealloc, there weren't any changes in iomem (which is probabl= y=20 okay result). With pci=3Drealloc, there seems to be some successful moves from 32-bit ->= =20 64-bit but something goes wrong with it in some other cases. I looked into the simplest case with problems. VF BARs only vanished=20 from 32-bit window, which I suppose is part of the correct behavior, but=20 never reappeared on 64-bit side. Here's the timestampless diff for convenience: --- /dev/fd/63=092026-09-30 16:01:19.364780770 +0300 +++ /dev/fd/62=092026-09-30 16:01:19.364780770 +0300 @@ -72,21 +72,45 @@ pci 0000:d7:00.0: bridge window [mem 0xee800000-0xeebfffff]: releasing pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored -pci 0000:d7:00.0: bridge window [mem size 0x00000000] to [bus d8-d9] add_s= ize 500000 add_align 100000 -pci 0000:d7:00.0: bridge window [mem 0xeed00000-0xef1fffff]: assigned -pci 0000:d8:00.0: ROM [mem 0xeed00000-0xeed7ffff pref]: assigned -pci 0000:d8:00.1: ROM [mem 0xeed80000-0xeedfffff pref]: assigned -pci 0000:d8:00.0: VF BAR 0 [mem 0xeee00000-0xeeefffff 64bit]: assigned -pci 0000:d8:00.0: VF BAR 3 [mem 0xeef00000-0xeeffffff 64bit]: assigned -pci 0000:d8:00.1: VF BAR 0 [mem 0xef000000-0xef0fffff 64bit]: assigned -pci 0000:d8:00.1: VF BAR 3 [mem 0xef100000-0xef1fffff 64bit]: assigned +pci 0000:d7:00.0: bridge window [mem size 0x00000000] to [bus d8-d9] add_s= ize 100000 add_align 100000 +pci 0000:d7:00.0: bridge window [mem 0xee800000-0xee8fffff]: assigned +pci 0000:d8:00.0: ROM [mem 0xee800000-0xee87ffff pref]: assigned +pci 0000:d8:00.1: ROM [mem 0xee880000-0xee8fffff pref]: assigned +pci 0000:d8:00.0: VF BAR 0 [mem size 0x00100000 64bit]: can't assign; no s= pace +pci 0000:d8:00.0: VF BAR 0 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.0: VF BAR 3 [mem size 0x00100000 64bit]: can't assign; no s= pace +pci 0000:d8:00.0: VF BAR 3 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.1: VF BAR 0 [mem size 0x00100000 64bit]: can't assign; no s= pace +pci 0000:d8:00.1: VF BAR 0 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.1: VF BAR 3 [mem size 0x00100000 64bit]: can't assign; no s= pace +pci 0000:d8:00.1: VF BAR 3 [mem size 0x00100000 64bit]: failed to assign +pci 0000:d8:00.0: ROM [mem 0xee800000-0xee87ffff pref]: releasing +pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.1: ROM [mem 0xee880000-0xee8fffff pref]: releasing +pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resource res= tored +pci 0000:d8:00.1: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.0: ROM [mem size 0x00080000 pref]: resource restored +pci 0000:d8:00.1: ROM [mem 0xee800000-0xee87ffff pref]: assigned +pci 0000:d8:00.0: ROM [mem 0xee880000-0xee8fffff pref]: assigned +pci 0000:d8:00.0: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resetting re= source +pci 0000:d8:00.0: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resetting re= source +pci 0000:d8:00.1: VF BAR 0 [mem 0x00000000-0x000fffff 64bit]: resetting re= source +pci 0000:d8:00.1: VF BAR 3 [mem 0x00000000-0x000fffff 64bit]: resetting re= source pci 0000:d7:00.0: PCI bridge to [bus d8-d9] -pci 0000:d7:00.0: bridge window [mem 0xeed00000-0xef1fffff] +pci 0000:d7:00.0: bridge window [mem 0xee800000-0xee8fffff] pci 0000:d7:00.0: bridge window [mem 0x207fff400000-0x207fffcfffff 64bit= pref] pci_bus 0000:d7: resource 4 [io 0xf000-0xffff window] pci_bus 0000:d7: resource 5 [mem 0xee800000-0xfbffffff window] pci_bus 0000:d7: resource 6 [mem 0x207000000000-0x207fffffffff window] -pci_bus 0000:d8: resource 1 [mem 0xeed00000-0xef1fffff] +pci_bus 0000:d8: resource 1 [mem 0xee800000-0xee8fffff] pci_bus 0000:d8: resource 2 [mem 0x207fff400000-0x207fffcfffff 64bit pref] pci 0000:d7:05.0: disabled boot interrupts on device [8086:2034] pci 0000:d8:00.0: CLS mismatch (128 !=3D 32), using 64 bytes The problems could be related to pci=3Drealloc not touching already assigne= d=20 bridge windows in many cases. pbus_size_mem() has resource_assigned()=20 check early so it won't size those bridge windows again. I've some=20 unfinished patch to remove that restriction but have been busy solving the= =20 recent set of regressions. Because VF BARs are optional resources, their failures are considered=20 acceptable so together with not trying to resize those windows, no=20 failures are detected by the fitting algorithm. There are a few cases that are more messy than the one above. I'll try to= =20 later look if they are fine or not. Annoyingly VF BARs are left with the=20 original base address when they fail, so they appear in lspci with what=20 looks a valid address but the corresponding resource is not in the=20 resource tree so it takes time to decipher if everything is properly=20 assigned or not (when things move around in iomem diffing it won't=20 easily tell it either). --=20 i. --8323328-683533231-1790792162=:1755 Content-Type: application/vnd.lotus-freelance; NAME=64bit.pre Content-Transfer-Encoding: BASE64 Content-ID: <7b479935-90ad-e272-0924-dac35814f8e0@linux.intel.com> Content-Description: Content-Disposition: ATTACHMENT; FILENAME=64bit.pre WyAgICA5LjY3MTA4Ml0gUENJIGhvc3QgYnJpZGdlIHRvIGJ1cyAwMDAwOmQ3 ClsgICAgOS42NzEwOTNdIHBjaV9idXMgMDAwMDpkNzogcm9vdCBidXMgcmVz b3VyY2UgW2lvICAweGYwMDAtMHhmZmZmIHdpbmRvd10KWyAgICA5LjY3MTA5 Nl0gcGNpX2J1cyAwMDAwOmQ3OiByb290IGJ1cyByZXNvdXJjZSBbbWVtIDB4 ZWU4MDAwMDAtMHhmYmZmZmZmZiB3aW5kb3ddClsgICAgOS42NzEwOTldIHBj aV9idXMgMDAwMDpkNzogcm9vdCBidXMgcmVzb3VyY2UgW21lbSAweDIwNzAw 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