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Fri, 4 Jul 2025 17:26:09 +0200 (CEST) Message-ID: Date: Fri, 4 Jul 2025 18:26:09 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] drm/rockchip: dw_hdmi_qp: Provide ref clock rate in dw_hdmi_qp_plat_data To: Maxime Ripard Cc: Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon , kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250704-rk3588-hdmi-cec-v1-0-2bd8de8700cd@collabora.com> <20250704-rk3588-hdmi-cec-v1-3-2bd8de8700cd@collabora.com> <20250704-granite-piculet-of-elevation-f01e08@houat> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: <20250704-granite-piculet-of-elevation-f01e08@houat> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Maxime, On 7/4/25 6:07 PM, Maxime Ripard wrote: > On Fri, Jul 04, 2025 at 05:23:24PM +0300, Cristian Ciocaltea wrote: >> In order to support correct initialization of the timer base in the HDMI >> QP IP block, extend the platform data to provide the necessary reference >> clock rate. >> >> While at it, ensure plat_data is zero-initialized in >> dw_hdmi_qp_rockchip_bind(). >> >> Signed-off-by: Cristian Ciocaltea >> --- >> drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 13 ++++++++++++- >> include/drm/bridge/dw_hdmi_qp.h | 1 + >> 2 files changed, 13 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c >> index 126e556025961e8645f3567b4d7a1c73cc2f2e7f..8c1185490009c5f1bc658998a868f8b18dc479a3 100644 >> --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c >> +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c >> @@ -431,8 +431,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, >> void *data) >> { >> struct platform_device *pdev = to_platform_device(dev); >> + struct dw_hdmi_qp_plat_data plat_data = {}; >> const struct rockchip_hdmi_qp_cfg *cfg; >> - struct dw_hdmi_qp_plat_data plat_data; >> struct drm_device *drm = data; >> struct drm_connector *connector; >> struct drm_encoder *encoder; >> @@ -515,6 +515,17 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, >> return ret; >> } >> >> + for (i = 0; i < ret; i++) { >> + if (!strcmp(clks[i].id, "ref")) { >> + plat_data.ref_clk_rate = clk_get_rate(clks[i].clk); >> + break; >> + } >> + } >> + if (!plat_data.ref_clk_rate) { >> + dev_err(hdmi->dev, "Missing ref clock\n"); >> + return -EINVAL; >> + } >> + > > You'd be better off not using clk_bulk, or calling an additional clk_get > for the ref clock only. I'd keep clk_bulk as there are 5 more clocks in the list. But replacing the loop with just an extra clk_get would be a simpler approach, indeed, so thanks for the hint! Regards, Cristian