From: Andi Kleen <ak@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
"Liang, Kan" <kan.liang@linux.intel.com>
Cc: acme@redhat.com, linux-kernel@vger.kernel.org,
alexander.shishkin@linux.intel.com,
Jianfeng Gao <jianfeng.gao@intel.com>,
Andrew Cooper <Andrew.Cooper3@citrix.com>
Subject: Re: [RESEND PATCH] perf/x86/intel: Fix unchecked MSR access error for Alder Lake N
Date: Mon, 22 Aug 2022 17:08:55 +0200 [thread overview]
Message-ID: <c09ba37c-f685-15a3-3042-8cb3a0f91282@linux.intel.com> (raw)
In-Reply-To: <YwOVJO05Ge8V9y5i@worktop.programming.kicks-ass.net>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2db93498ff71..232e24324fd7 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4473,6 +4473,11 @@ static bool init_hybrid_pmu(int cpu)
> struct x86_hybrid_pmu *pmu = NULL;
> int i;
>
> + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
> + pr_warn_once("hybrid PMU and virt are incompatible\n");
> + return false;
> + }
It's totally possible to virtualize hybrid correctly, so I don't think
this is justified
-Andi
next prev parent reply other threads:[~2022-08-22 15:14 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 18:15 kan.liang
2022-08-19 8:05 ` Peter Zijlstra
2022-08-19 8:33 ` Peter Zijlstra
2022-08-22 13:24 ` Liang, Kan
2022-08-22 13:55 ` Peter Zijlstra
2022-08-22 15:20 ` Liang, Kan
2022-08-19 14:38 ` Peter Zijlstra
2022-08-22 13:28 ` Liang, Kan
2022-08-22 13:48 ` Peter Zijlstra
2022-08-22 14:31 ` Andi Kleen
2022-08-22 14:39 ` Peter Zijlstra
2022-08-22 14:51 ` Andrew Cooper
2022-08-22 14:59 ` Liang, Kan
2022-08-22 15:21 ` Peter Zijlstra
2022-08-22 15:08 ` Andi Kleen [this message]
2022-08-22 15:47 ` Peter Zijlstra
2022-08-22 18:21 ` Sean Christopherson
2022-08-22 19:21 ` Andi Kleen
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