Re: [PATCH] riscv: add ARCH_DMA_MINALIGN support

[Xianting TIan <xianting.tian@linux.alibaba.com>]

在 2021/8/9 上午12:30, Jisheng Zhang 写道:
> On Sat,  7 Aug 2021 22:55:37 +0800
> Xianting Tian <xianting.tian@linux.alibaba.com> wrote:
>
>> Introduce ARCH_DMA_MINALIGN to riscv arch.
>>
>> Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
>> ---
>>   arch/riscv/include/asm/cache.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
>> index 9b58b1045..2945bbe2b 100644
>> --- a/arch/riscv/include/asm/cache.h
>> +++ b/arch/riscv/include/asm/cache.h
>> @@ -11,6 +11,8 @@
>>   
>>   #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
>>   
>> +#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
> It's not a good idea to blindly set this for all riscv. For "coherent"
> platforms, this is not necessary and will waste memory.

I checked ARCH_DMA_MINALIGN definition,  "If an architecture isn't fully 
DMA-coherent, ARCH_DMA_MINALIGN must be set".

so that the memory allocator makes sure that kmalloc'ed buffer doesn't 
share a cache line with the others.

Documentation/core-api/dma-api-howto.rst

2) ARCH_DMA_MINALIGN

    Architectures must ensure that kmalloc'ed buffer is
    DMA-safe. Drivers and subsystems depend on it. If an architecture
    isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in
    the CPU cache is identical to data in main memory),
    ARCH_DMA_MINALIGN must be set so that the memory allocator
    makes sure that kmalloc'ed buffer doesn't share a cache line with
    the others. See arch/arm/include/asm/cache.h as an example.

    Note that ARCH_DMA_MINALIGN is about DMA memory alignment
    constraints. You don't need to worry about the architecture data
    alignment constraints (e.g. the alignment constraints about 64-bit
    objects).

>
>> +
>>   /*
>>    * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
>>    * the flat loader aligns it accordingly.