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Wed, 07 Jan 2026 05:17:38 -0800 (PST) Message-ID: Date: Wed, 7 Jan 2026 15:17:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 8/8] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks To: Biju Das , "vkoul@kernel.org" , Fabrizio Castro , "geert+renesas@glider.be" , Prabhakar Mahadev Lad Cc: "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Claudiu Beznea References: <20251223134952.460284-1-claudiu.beznea.uj@bp.renesas.com> <20251223134952.460284-9-claudiu.beznea.uj@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, Biju, On 12/23/25 16:43, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Claudiu >> Sent: 23 December 2025 13:50 >> Subject: [PATCH v6 8/8] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks >> >> From: Claudiu Beznea >> >> Add support for device_{pause, resume}() callbacks. These are required by the RZ/G2L SCIFA driver. >> >> Signed-off-by: Claudiu Beznea >> --- >> >> Changes in v6: >> - set CHCTRL_SETSUS for pause and CHCTRL_CLRSUS for resume >> - dropped read-modify-update approach for CHCTRL updates as the >> HW returns zero when reading CHCTRL >> - moved the read_poll_timeout_atomic() under spin lock to >> ensure avoid any races b/w pause and resume functionalities >> >> Changes in v5: >> - used suspend capability of the controller to pause/resume >> the transfers >> >> drivers/dma/sh/rz-dmac.c | 36 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 44f0f72cbcf1..377bdd5c9425 >> 100644 >> --- a/drivers/dma/sh/rz-dmac.c >> +++ b/drivers/dma/sh/rz-dmac.c >> @@ -135,10 +135,12 @@ struct rz_dmac { >> #define CHANNEL_8_15_COMMON_BASE 0x0700 >> >> #define CHSTAT_ER BIT(4) >> +#define CHSTAT_SUS BIT(3) >> #define CHSTAT_EN BIT(0) >> >> #define CHCTRL_CLRINTMSK BIT(17) >> #define CHCTRL_CLRSUS BIT(9) >> +#define CHCTRL_SETSUS BIT(8) >> #define CHCTRL_CLRTC BIT(6) >> #define CHCTRL_CLREND BIT(5) >> #define CHCTRL_CLRRQ BIT(4) >> @@ -827,6 +829,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, >> return status; >> } >> >> +static int rz_dmac_device_pause(struct dma_chan *chan) { >> + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); >> + u32 val; >> + int ret; >> + >> + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > >> + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); > > > Probably first you need to check CHSTAT_EN first before setting CHCTRL_SETSUS?? > > As per the hardware manual > > " > Suspends the current DMA transfer. Setting this bit to 1 when 1 is set in EN of the > CHSTAT_n/nS register can suspend the current DMA transfer." OK, I'll update it as follows: static int rz_dmac_device_pause(struct dma_chan *chan) { struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); u32 val; guard(spinlock_irqsave)(&channel->vc.lock); val = rz_dmac_ch_readl(channel, CHSTAT, 1); if (!(val & CHSTAT_EN)) return 0; rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); return read_poll_timeout_atomic(rz_dmac_ch_readl, val, (val & CHSTAT_SUS), 1, 1024, false, channel, CHSTAT, 1); } This avoids timeouts reported by read_poll_timeout_atomic() when pause is set for a disabled channel. > > >> + ret = read_poll_timeout_atomic(rz_dmac_ch_readl, val, >> + (val & CHSTAT_SUS), 1, 1024, >> + false, channel, CHSTAT, 1); >> + } >> + >> + return ret; >> +} >> + >> +static int rz_dmac_device_resume(struct dma_chan *chan) { >> + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); >> + u32 val; >> + int ret; >> + >> + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > > >> + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); > > > Similarly, first you need to check CHSTAT_SUS bit first and then clear suspend state. > > > Clears the suspend status. Setting this bit to 1 when 1 is set in SUS of the > CHSTAT_n/nS register can clear the suspend status. I'll update this one as follows, to keep the code simple: static int rz_dmac_device_resume(struct dma_chan *chan) { struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); u32 val; guard(spinlock_irqsave)(&channel->vc.lock); /* Do not check CHSTAT_SUS but rely on HW capabilities. */ rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); return read_poll_timeout_atomic(rz_dmac_ch_readl, val, !(val & CHSTAT_SUS), 1, 1024, false, channel, CHSTAT, 1); } With this: 1/ in case the channel is not suspended and the CHCTRL_CLRSUS is set, the read_poll_timeout_atomic() will not timeout, as the default value of the CHSTAT_SUS is zero. 2/ in case the channel is suspended and the CLRSUS is set, it is behaving as expected but without an extra check of the CHSTAT_SUS bit before setting CHCTRL_CLRSUS. Thank you, Claudiu