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X-CSE-ConnectionGUID: aY8svbsLRA2D/5IMKA8XyA== X-CSE-MsgGUID: WrFCTmKyTgu7nl6pDiPR5w== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="41273573" X-IronPort-AV: E=Sophos;i="6.14,220,1736841600"; d="scan'208";a="41273573" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 07:24:34 -0800 X-CSE-ConnectionGUID: mdKDqChQTJqGu5Eny0WrvA== X-CSE-MsgGUID: adTTfgKcQEaR1dxZeWjN9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,220,1736841600"; d="scan'208";a="123527461" Received: from kinlongk-desk.amr.corp.intel.com (HELO [10.125.109.94]) ([10.125.109.94]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 07:24:33 -0800 Message-ID: Date: Tue, 4 Mar 2025 07:24:51 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 11/13] x86/mm: do targeted broadcast flushing from tlbbatch code To: Borislav Petkov Cc: Rik van Riel , x86@kernel.org, linux-kernel@vger.kernel.org, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org References: <20250226030129.530345-1-riel@surriel.com> <20250226030129.530345-12-riel@surriel.com> <20250303114618.GBZ8WWihMDjf-oy8P0@fat_crate.local> <7e1ca8c7-6f3e-44dc-9dd8-bd273a03a83e@intel.com> <20250304115207.GFZ8bpZ83u7L9x43Rq@fat_crate.local> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 3/4/25 03:52, Borislav Petkov wrote: > On Mon, Mar 03, 2025 at 01:47:42PM -0800, Dave Hansen wrote: ... > IOW, this: > > /* Flush all mappings for a given PCID, not including globals. */ > static inline void __invlpgb_flush_single_pcid_nosync(unsigned long pcid) > { > __invlpgb(0, pcid, 0, 1, 0, INVLPGB_PCID); > cpu_set_tlbsync(true); > } > > Right? Yep, that works. Optimizing out the writes like the old code did is certainly a good thought. But I suspect the cacheline is hot the majority of the time. >>> static void broadcast_tlb_flush(struct flush_tlb_info *info) >>> { >>> bool pmd = info->stride_shift == PMD_SHIFT; >>> @@ -790,6 +821,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, >>> if (IS_ENABLED(CONFIG_PROVE_LOCKING)) >>> WARN_ON_ONCE(!irqs_disabled()); >>> >>> + tlbsync(); >> >> This one is in dire need of comments. > > Maybe this: > > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c > index 08672350536f..b97249ffff1f 100644 > --- a/arch/x86/mm/tlb.c > +++ b/arch/x86/mm/tlb.c > @@ -822,6 +822,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, > if (IS_ENABLED(CONFIG_PROVE_LOCKING)) > WARN_ON_ONCE(!irqs_disabled()); > > + /* > + * Finish any remote TLB flushes pending from this CPU: > + */ > tlbsync(); That's a prototypical "what" comment and not "why", though. It makes a lot of sense that any flushes that the old task did should complete before a new gets activated. But I honestly can't think of a _specific_ problem that it causes. I don't doubt that this does _some_ good, but I just don't know what good it does. ;)