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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: N9E+Ion7kWcDR8APq6Lpl1M3mym2GHEmCxQ+86J9yq+OrE37lNTZ49qEEBfMHfc5Lbtadi/8vXaTzD4ArrOnZZUYwV+M4NiSpYw0fxnoBG+Ls9X7kcAB0/M+o5vgCCZHk44MqO6s4ygTkObjJkI9/wOvJa05M1M9j1U77kI/F4rcosaAZ6V7O3PqUVT9STEm3dY2JaKMHetpBARY5jRP4VCQlvFJS4q9FSJ1QW6sLUH+Q7P0qT8KVvPxTSEGqFplJbpB2RkvRd83l7GkHV6gSIe6/JGRRfDPVRmeCJQeBQSeBdAyADDoefHxFJLNiwO2fqhs4NLvs34KFiqV+djmIZxHYMyI10Owyr9nXMqCm+s/97pt9RWmmBy6BWNw1wYULsvyuB+jLuBM2CNfdpgWw0QjdCURwHl/WemoxVnwHONPZWF6sxBKW2QWuxQa1TKE X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2026 07:44:46.8427 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 429c23cf-62a9-44f9-8440-08df2a902f75 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: ZR1PEPF0000E464.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9759 Hi, On 2026. 10. 14. 17:38, Andre Przywara wrote: >> +static int smccc_cache_probe(struct arm_smccc_device *sdev) >> +{ >> +    struct arm_smccc_res res = {}; >> +    struct smccc_cache *cache; >> +    int ret; >> + >> +    arm_smccc_1_1_invoke(sdev->func_id, &res); > > I think you should provide the explicit function ID name here, and not > rely on which function exactly is used to probe for the interface's > existence. I thought that was the point of the matcher, that you could in theory assign the same probe handler to any function ID? For example if there's some FW that implements this (or a compatible) function, but at a different ID, you would only update the match table? At least that's how most subsystems (I2C, PCI, USB) do it. >> +    if ((s32)res.a0) >> +        return -ENODEV; >> + >> +    cache = cache_coherency_ops_instance_alloc(&smccc_cache_ops, >> +                           struct smccc_cache, cci); >> +    if (!cache) >> +        return -ENOMEM; >> + >> +    mutex_init(&cache->lock); >> +    cache->latency_us = lower_32_bits(res.a2); >> +    cache->rate_limit = res.a3; > > According to the spec you would need lower_32_bits() for a3 as well - if > we are going to use this value. But I don't think we need to, see above. Where does it say that? My copy of DEN 0028 1.7 H, released 2026/Jul/24, only says the following: X3 (uint64_t attr_2) Rate Limit: The maximum number of SMCCCC_ARCH_CLEAN_INV_MEMREGION calls allowed per second. If set to 0, it indicates that this field is not reported by the implementation. See my second-to-last comment on v2 of this patch: https://lore.kernel.org/lkml/591e7ac9-310e-40f4-ab22-161d6ea8f487@arm.com/ Maybe I have an outdated copy already? ;_; Bence