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Tue, 27 Oct 2026 05:15:03 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd4e89dbsm432825166b.18.2026.10.27.05.15.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2026 05:15:02 -0700 (PDT) Message-ID: Date: Tue, 27 Oct 2026 13:14:59 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] clk: qcom: Add SM7250 graphics clock controller driver To: patches@brar.si, Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Imran Shaik Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261027-gpucc-sm7250-v2-0-773056e4043e@brar.si> <20261027-gpucc-sm7250-v2-2-773056e4043e@brar.si> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261027-gpucc-sm7250-v2-2-773056e4043e@brar.si> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDA0OCBTYWx0ZWRfX+unpNlYYkCzK 9TxIB1W4qklZSgxaOCSYmatHh5L+2YNBtBrEFc/eowPbukbkhHmAr8Jtjb8K7Wqd34O8j5scpHL Ot2Wu2Qnl6BywBdNhhgKmUo1ncKu+kI= X-Authority-Analysis: v=2.4 cv=bsnZl0ai c=1 sm=1 tr=0 ts=6ae095c9 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=2zQhOlC99_H9tdcWL1cA:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-ORIG-GUID: lAvjUk-v5F01vNJoXWJnbCFEjVIXGgpx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDA0OCBTYWx0ZWRfX7PWuUv/0GYgE 2ngC0zvRaDeCZSfhjSWHlJiOO2BjQDt3ZVBf7YxsWk5jhRzwdr916f7WlBOKKOwHghyykw4qvi4 ltrDOCyiJ2zAkAIjeJHJy2QjJye7hPQOVHG4gAvZ1G5TwE8o6NnVcDsZe+Jzf2HgA+INIoWSpGk nrD27U0HeirDTEm/z5GjqIxaAascc20r1ugb+sFF7gTyJbpMyvL00taaaLXnAaJUsUv2ugTM4H+ W0DqD/POLcTR956gxymh4gvMn5Kk64cbsY9KEIT5EvgN5y9WDvpF009sBTiUfieCL+YVelbP61p tZGBEgSF2xRMIWL1pnn7DXdPtTyTQPISCzfvubSih0RVsnWt3fIyaMTIEQMqfJCaANj9xSVa5gq sP/hZHrHWngSeHkJTwd1WoE58ZyoYMFkHcObxDSTvYoWLQer+Zb9sgG9fy6JYePYKUJczBJK68L FnpJd5L10o4QmmrUqwg== X-Proofpoint-GUID: lAvjUk-v5F01vNJoXWJnbCFEjVIXGgpx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-27_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270048 On 10/27/26 5:35 AM, Ishu Brar via B4 Relay wrote: > From: Ishu Brar > > Add a driver for the graphics clock controller of the Qualcomm SM7250 > SoC (Snapdragon 765/765G/768G). It provides the GMU clock and its PLL, > the GPU CX and GX power domains, and the GPU SMMU vote clock. The layout > follows the SM8250 driver, since both use a Lucid PLL and the same GMU > clock setup; the PLL settings, frequency table, register offsets and > GDSC data come from the downstream driver of the platform. [...] > +#define CX_GMU_CBCR_SLEEP_MASK 0xf > +#define CX_GMU_CBCR_SLEEP_SHIFT 4 > +#define CX_GMU_CBCR_WAKE_MASK 0xf > +#define CX_GMU_CBCR_WAKE_SHIFT 8 #define CX_GMU_CBCR_SLEEP_MASK GENMASK(7, 4) #define CX_GMU_CBCR_WAKE_MASK GENMASK(11, 8) [...] > +static void gpu_cc_sm7250_regs_configure(struct device *dev, struct regmap *regmap) > +{ > + unsigned int value, mask; > + > + /* > + * Configure gpu_cc_cx_gmu_clk with recommended > + * wakeup/sleep settings > + */ > + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; > + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; > + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; > + regmap_update_bits(regmap, 0x1098, mask, value); and then here: mask = CX_GMU_CBCR_WAKE_MASK | CX_GMU_CBCR_SLEEP_MASK; value = FIELD_PREP(CX_GMU_CBCR_WAKE_MASK, 0xf) | FIELD_PREP(CX_GMU_CBCR_SLEEP_MASK, 0xf); regmap_update_bits(regmap, 0x1098, mask, value); you'll also want .use_rpm in the desc struct Konrad