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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454a997b1ecsm58921595e9.11.2025.07.04.08.37.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Jul 2025 08:37:36 -0700 (PDT) Message-ID: Date: Fri, 4 Jul 2025 16:37:35 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] arm64: dts: qcom: x1e80100: Add videocc To: Stephan Gerhold , Bjorn Andersson Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Jagadeesh Kona , Konrad Dybcio , Abel Vesa , Johan Hovold , Stefan Schmidt , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250701-x1e-videocc-v1-0-785d393be502@linaro.org> <20250701-x1e-videocc-v1-6-785d393be502@linaro.org> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250701-x1e-videocc-v1-6-785d393be502@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 01/07/2025 18:28, Stephan Gerhold wrote: > Add the video clock controller for X1E80100, similar to sm8550.dtsi. It > provides the needed clocks/power domains for the iris video codec. > > Signed-off-by: Stephan Gerhold > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index a9a7bb676c6f8ac48a2e443d28efdc8c9b5e52c0..890eaaa40184a18bff54f2d750968112a2546d19 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5,6 +5,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -5171,6 +5172,20 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + videocc: clock-controller@aaf0000 { > + compatible = "qcom,x1e80100-videocc"; > + reg = <0 0x0aaf0000 0 0x10000>; > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_QMIP_VIDEO_VCODEC_AHB_CLK>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,x1e80100-mdss"; > reg = <0 0x0ae00000 0 0x1000>; > Reviewed-by: Bryan O'Donoghue