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Thu, 9 Apr 2026 12:47:12 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , Subject: [PATCH rc v1 3/4] iommu/arm-smmu-v3: Retain SMMUEN during kdump device reset Date: Thu, 9 Apr 2026 12:46:52 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D4:EE_|DSVPR12MB999192:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f7f8777-30de-40e6-1b87-08de9670d309 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|7416014|82310400026|1800799024|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 60LccGDMmAWk2MQGqR9kuez4Yj6uxrgAOMQ9EHqhOCqnYQBIacpOeA+kbQn/tVfwQDGIOjoIkubZlSMb4mCC8KxG5G9yH2cWu2px75V/MKdL2VKTmjThXw34MQSGN8aMCrj+0oTGMd7NwMRqwWVaKvGIXZ4Ogi8vcCDwWxgzqMN1lOFuHsqMcMkVRf6mr+Ai9zzvf/MyDrcTqWficmBiH5StUKtT5O6OB/Ky5OklVeRz+M22n3W+BoWENisVtxTmLLtom/B2Yp7YmZQIgceQHppSvVnQVfLPrvx7NAkZ/5b0ZBiKlhpCoAgAkDW3QcbA9QxyezdguvxdRm55VIGmcS2y06ExhiWI8n61lfGabX8vnWGHU5i/VGtUMZYEy6dOgWdU5Zm4H11H5QaBzQhRbvcXVjQosSejmexMtiBzuMUMAKX3TzNuo+L0tTJUFs3LYfrQJlKjJN2FoV3oeGRBDYcs4Xv/kmnM8ysUtTcqoA18cRChQPjtlSkZLXU4YQ0Q86ez82i0mhgsdY4Cq6O0j2dBQA/qSvS3oWTFqh9KIc+uChyWiZ4PhONHnv7lNflPn0mJ2m0QYaBIOF6MGXGsN01lQsyM/AVb2+h7q5zMhXH8hWJlOWgdf86uPo5ksrdd1ZHfpLUORkP0ziiVHTOMsnZvZ+05E9pc1N1tY8MbfejHdtI8okzLHN5oWZjjbsGC91MQERQMo6h4Sgo4bhd8UZh8rAnipa9wFosiwQsBHMySNhOIniTU8KKnnmcmN9uB3OFM+SAJMW72iQaH00KvJQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(7416014)(82310400026)(1800799024)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0zlzX59H6lXZZyUSCoOWklLsNWfYa+5gd/D6L0SseOpTAnJubkxkGD05duqXnoENgKjuM50GpcnDKDApt6yOrXNTiFVKFUNwr+uuXcyEHyaMwr6S2ZbAyMSCS8DERQf3BP15fOCImUJ3ZWtC63gsqWQULwTOA49EEjhikbVwNseuQrOviLshbDMkPt11v0vecmcobYkQpCUsJ3kJjbIun4czTmYo9zMcuzuqQqHqkeY5LMQVYDZpoFgMsASyAkhqUFgAkWJBnT6EpIp5KosM+6n3yfYjiiJhCJA3dpSXx5vtXEZvsJCBNorkXyR4WjOS/7QRaV3e6kLH8KGDWMFp2PkD2xjIAisVewSFuabyXhIpvlFHZPnCoSWvuvHFtOtKlObxNfUap/ZrJpXlnFoX70ibyzaMEmQGgVBziK1PlsD3qIHLiyRU1tU26m+QlZDe X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 19:47:25.3880 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f7f8777-30de-40e6-1b87-08de9670d309 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DSVPR12MB999192 When ARM_SMMU_OPT_KDUMP is set, skip the GBPA/disable/CR1/CR2/STRTAB_BASE update sequence in arm_smmu_device_reset(). Those register writes are all CONSTRAINED UNPREDICTABLE while SMMUEN==1, so leaving them untouched lets in-flight DMA continue to be translated by the adopted stream table. Initialize 'enables' to 0 so it can carry CR0_SMMUEN in kdump case. Then, preserve that when enabling the command queue. Also add a comment explaining why EVTQ/PRIQ are disabled in kdump cases. Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 +++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index ff3c1beb3739e..d0ef8fb876978 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4931,13 +4931,28 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables = 0; struct arm_smmu_cmdq_ent cmd; /* Clear CR0 and sync (disables SMMU and queue processing) */ reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); if (reg & CR0_SMMUEN) { dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); + + /* + * In a kdump case, retain SMMUEN to avoid transiently aborting + * in-flight DMA. According to spec, updating STRTAB_BASE, CR1, + * or CR2 while SMMUEN==1 is CONSTRAINED UNPREDICTABLE. So skip + * those register updates and rely on the adopted stream table + * from the crashed kernel. + */ + if (smmu->options & ARM_SMMU_OPT_KDUMP) { + dev_info(smmu->dev, + "kdump: retaining SMMUEN for in-flight DMA\n"); + enables = CR0_SMMUEN; + goto reset_queues; + } + arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); } @@ -4965,12 +4980,23 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Stream table */ arm_smmu_write_strtab(smmu); +reset_queues: + if (smmu->options & ARM_SMMU_OPT_KDUMP) { + /* Disable queues since arm_smmu_device_disable() was skipped */ + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to disable queues\n"); + return ret; + } + } + /* Command queue */ writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); - enables = CR0_CMDQEN; + enables |= CR0_CMDQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { @@ -5038,6 +5064,11 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + /* + * Disable EVTQ and PRIQ in kdump kernel. The old kernel's CDs and page + * tables may be corrupted, which could trigger event spamming. PRIQ is + * also useless since we cannot service page requests during kdump. + */ if (is_kdump_kernel()) enables &= ~(CR0_EVTQEN | CR0_PRIQEN); -- 2.43.0