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From: "Yicong Yang" <yang.yicong@picoheart.com>
To: <hu.shengming@zte.com.cn>, <pjw@kernel.org>, <palmer@dabbelt.com>,
	 <aou@eecs.berkeley.edu>
Cc: <yang.yicong@picoheart.com>, <alex@ghiti.fr>,
	 <akpm@linux-foundation.org>, <baolin.wang@linux.alibaba.com>,
	 <wangruikang@iscas.ac.cn>, <linux-riscv@lists.infradead.org>,
	 <linux-kernel@vger.kernel.org>, <zhang.run@zte.com.cn>,
	 <luo.haiyang@zte.com.cn>
Subject: Re: [PATCH] riscv: mm: Limit per-page TLB flushes for large PTE batches
Date: Thu, 12 Nov 2026 16:21:19 +0800	[thread overview]
Message-ID: <c125c25d-c7be-4116-9837-09dd7fa91a91@picoheart.com> (raw)
In-Reply-To: <20261112110525378dgDlKhA-G74_y3b6ZeZkz@zte.com.cn>

On 11/12/26 11:05 AM, hu.shengming@zte.com.cn wrote:
> From: Shengming Hu <hu.shengming@zte.com.cn>
> 
> On systems without Svvptc, update_mmu_cache_range() performs one local
> TLB invalidation per PTE. With 4 KiB pages, installing a PTE-mapped
> 1 MiB anonymous folio requires 256 SFENCE.VMA instructions, or 256
> SINVAL.VMA instructions bracketed by SFENCE.W.INVAL and
> SFENCE.INVAL.IR.
> 
> Apply the existing local TLB range-flush policy to PTE batch updates.
> When nr exceeds tlb_flush_all_threshold, use local_flush_tlb_all_asid()
> to replace per-page invalidations with a single ASID-wide SFENCE.VMA.
> This orders the PTE writes before subsequent implicit page-table
> accesses and invalidates translations for the entire batch. As with
> range flushes, this may also evict unrelated translations for the same
> ASID.
> 
> Benchmark results from will-it-scale's page_fault1_processes under
> QEMU 9.1.93 (qemu-9.2.0-0.3.rc3.fc40), with svvptc=false and
> CONFIG_TRANSPARENT_HUGEPAGE=y (higher is better):
> 
> Folio size      Before       After     Change
> =============================================
> 4 KiB           116537      113503      -2.6%
> 512 KiB        1431962     1977519     +38.1%
> 1 MiB          1528457     2208209     +44.5%
> 
> Signed-off-by: Shengming Hu <hu.shengming@zte.com.cn>
> ---
>  arch/riscv/include/asm/pgtable.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 2ebd5fa5adc5..ebe42fcf35ae 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -571,6 +571,11 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf,
>  	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC))
>  		return;
> 
> +	if (nr > tlb_flush_all_threshold) {
> +		local_flush_tlb_all_asid(asid);
> +		return;
> +	}
> +

could we reuse local_flush_tlb_range_threshold_asid() or
local_flush_tlb_range_asid()? now the logic is exactly
the same.

thanks.

>  	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)) {
>  		local_sfence_w_inval();
>  		while (nr--)

  reply	other threads:[~2026-11-12  8:21 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-12  3:05 hu.shengming
2026-11-12  8:21 ` Yicong Yang [this message]
2026-11-12 12:00 ` Jisheng Zhang

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