From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 24F491A9B53; Sun, 27 Apr 2025 14:27:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745764076; cv=none; b=CzMQ7QXIyoj4SPhQBzqosciqQVdfTmN4rprQOckNsw/hWsFED6Kamtm4/pdhdcm94ok5UevYGV7SFkys93/CqirLq78DWCIOj3nQW2PljW82U0Jev48ar3gtghHN3TqdJ8EXBaXdNillMtat+3vk1OkpJp4D+mire5eeIyB8If8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745764076; c=relaxed/simple; bh=ZQTTJ8FIBhozJKse5Fs8qRc9zjDXqQ6FkY5VyfEabDE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=i7OOENRCfkbE7L8ZIlP803ERvti0DPE/jkGM55B8X57cb/UsxWOJRw3kY6tP3C5i4LVWGifmCEQ6FQ3dznRS/KejN3OuteD6EmxFqG0ThvipRENt/EBdKvNyNNNAdFe7+EuWyKdxpJ9IfKrXbXqJh70nGO0qZ3It1uXmxh0GAC4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=TqUXsezz; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="TqUXsezz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=Message-ID:Date:MIME-Version:Subject:From: Content-Type; bh=6hi3ytW2JJOVFOaND+zNAN3cQVQYz5DqcVtZd66jYcc=; b=TqUXsezzrI68t0pq8SAyOPLMcSZPD/TOy9nhOxYI1Pxb9h73VjBklZt2FnMyLb /yOdzzwpq7iocWGZnF1CR6arfo9YsdKOLHb4KSNxzWdC+fP/le8rPRAwSZSqVkD7 cN4XPeeAtY5hlEmypu149GH+lqLQ7fbvcP00fSGqnqVy8= Received: from [192.168.71.89] (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wA3jySSPg5ofRKLCw--.19505S2; Sun, 27 Apr 2025 22:26:27 +0800 (CST) Message-ID: Date: Sun, 27 Apr 2025 22:26:26 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] PCI: dw-rockchip: Reorganize register and bitfield definitions To: Manivannan Sadhasivam Cc: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Niklas Cassel References: <20250427125316.99627-1-18255117159@163.com> <20250427125316.99627-3-18255117159@163.com> Content-Language: en-US From: Hans Zhang <18255117159@163.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID:_____wA3jySSPg5ofRKLCw--.19505S2 X-Coremail-Antispam: 1Uf129KBjvJXoW3Wr13Ww18try3uF1DCFykZrb_yoW7Xr47pa 4DAa4Ikr45t3y7Z3sY9F98ZFWIqrnxKFWUGrs3K3y8u3WkAw18Gr1jgF95Wry7Jr4kAryf uwn8u34xWFWakrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UBrWwUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhw8o2gOIurF2wACsL On 2025/4/27 22:14, Manivannan Sadhasivam wrote: > On Sun, Apr 27, 2025 at 08:53:15PM +0800, Hans Zhang wrote: >> Register definitions were scattered with ambiguous names (e.g., >> PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked >> hierarchical grouping. Magic values for bit operations reduced code >> clarity. >> >> Group registers and their associated bitfields logically. This improves >> maintainability and aligns the code with hardware documentation. >> >> Signed-off-by: Hans Zhang <18255117159@163.com> >> Reviewed-by: Niklas Cassel >> Reviewed-by: Manivannan Sadhasivam >> --- >> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 49 ++++++++++++------- >> 1 file changed, 31 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> index e7d33d545d5b..a778f4f61595 100644 >> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >> @@ -33,24 +33,37 @@ >> >> #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) >> >> -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> -#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 >> -#define PCIE_CLIENT_INTR_MASK_MISC 0x24 >> -#define PCIE_SMLH_LINKUP BIT(16) >> -#define PCIE_RDLH_LINKUP BIT(17) >> -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) >> -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 >> +/* General Control Register */ >> +#define PCIE_CLIENT_GENERAL_CON 0x0 > > Is this the actual name of the register as per the documentation? Just asking > because of '_CON' instead of '_CONTROL'. > Hi Mani, Yes. I saw that RK3588 TRM is named like this. PCIE_CLIENT_GENERAL_CON Best regards, Hans > - Mani > >> +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) >> +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) >> +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) >> +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) >> + >> +/* Interrupt Status Register Related to Legacy Interrupt */ >> #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 >> + >> +/* Interrupt Status Register Related to Miscellaneous Operation */ >> +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 >> +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) >> +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) >> + >> +/* Interrupt Mask Register Related to Legacy Interrupt */ >> #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c >> + >> +/* Interrupt Mask Register Related to Miscellaneous Operation */ >> +#define PCIE_CLIENT_INTR_MASK_MISC 0x24 >> + >> +/* Hot Reset Control Register */ >> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 >> +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) >> + >> +/* LTSSM Status Register */ >> #define PCIE_CLIENT_LTSSM_STATUS 0x300 >> -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) >> -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) >> +#define PCIE_SMLH_LINKUP BIT(16) >> +#define PCIE_RDLH_LINKUP BIT(17) >> +#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) >> +#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) >> >> struct rockchip_pcie { >> struct dw_pcie pci; >> @@ -161,13 +174,13 @@ static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) >> static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) >> { >> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, >> - PCIE_CLIENT_GENERAL_CONTROL); >> + PCIE_CLIENT_GENERAL_CON); >> } >> >> static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) >> { >> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, >> - PCIE_CLIENT_GENERAL_CONTROL); >> + PCIE_CLIENT_GENERAL_CON); >> } >> >> static int rockchip_pcie_link_up(struct dw_pcie *pci) >> @@ -516,7 +529,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, >> rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); >> >> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, >> - PCIE_CLIENT_GENERAL_CONTROL); >> + PCIE_CLIENT_GENERAL_CON); >> >> pp = &rockchip->pci.pp; >> pp->ops = &rockchip_pcie_host_ops; >> @@ -562,7 +575,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev, >> rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); >> >> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, >> - PCIE_CLIENT_GENERAL_CONTROL); >> + PCIE_CLIENT_GENERAL_CON); >> >> rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; >> rockchip->pci.ep.page_size = SZ_64K; >> -- >> 2.25.1 >> >