From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,T_DKIM_INVALID autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA67BECE560 for ; Mon, 17 Sep 2018 18:32:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 447D0214DA for ; Mon, 17 Sep 2018 18:32:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="KmyWuJ58" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 447D0214DA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728080AbeIRABF (ORCPT ); Mon, 17 Sep 2018 20:01:05 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:34476 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727089AbeIRABE (ORCPT ); Mon, 17 Sep 2018 20:01:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1537209152; x=1568745152; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=osACigfG3tyoWZe0zxiSAjdhGvyjCfyNb7gzwub1hzE=; b=KmyWuJ586kqvessW+cMIFZk1nG7u0YWoxwiMrhKJEWQfiZT8VwSNP/CY vpDszvWLcxAgTkBJNOBCR9ZHqB8jHv+ZTitLTQoCXL9FWdYhmzOWcTzx/ yxlW2k7qgDNbBR5uJ4E2DBzaOe6gQKo/E4Kyb4zjTY+7DFE6tCM0niOWU wqgBTWtZGu09/u3OGvU3vV/UfGT8KZA9dQW27Xk6fFID+otE4vKZNnY9w aXTdZISxw1NWtb5zG6SSarGCntaR7TIWrKQZvylQrkMgMYruRrnYnEmQH PY3yHJrqfoVWWSmI+QRXi/K3WPDWg9pHH7Eyd+JoVKk7ms1jG8qjtsZ+e A==; X-IronPort-AV: E=Sophos;i="5.53,386,1531756800"; d="scan'208";a="89931325" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 18 Sep 2018 02:32:32 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 17 Sep 2018 11:18:53 -0700 Received: from c02v91rdhtd5.sdcorp.global.sandisk.com (HELO [10.196.159.148]) ([10.196.159.148]) by uls-op-cesaip02.wdc.com with ESMTP; 17 Sep 2018 11:32:31 -0700 Subject: Re: [RFC 3/3] RISC-V: Remove per cpu clocksource To: Christoph Hellwig , Thomas Gleixner Cc: "palmer@sifive.com" , "linux-riscv@lists.infradead.org" , "mark.rutland@arm.com" , "robh@kernel.org" , Damien Le Moal , "marc.zyngier@arm.com" , "anup@brainfault.org" , "linux-kernel@vger.kernel.org" References: <1536962096-233842-1-git-send-email-atish.patra@wdc.com> <1536962096-233842-4-git-send-email-atish.patra@wdc.com> <20180917143550.GC15588@infradead.org> <20180917150149.GA25348@infradead.org> From: Atish Patra Message-ID: Date: Mon, 17 Sep 2018 11:32:31 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180917150149.GA25348@infradead.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/17/18 8:01 AM, Christoph Hellwig wrote: > On Mon, Sep 17, 2018 at 04:52:44PM +0200, Thomas Gleixner wrote: >> If this really does not need configuration and all actual implementations >> are not "allowed" to screw the timer up, then this surely can do without >> DT. > > That would be the plan. > >> >> Just for the record, this would be the first (architected) timer ever which >> just works. I'm having a hard time to believe this, but I'd certainly >> welcome it. > > And that would be the contact with reality. Note that the current > scheme which just matches for the riscv hart (aka cpu core) nodes > would not exactly help either. > I thought we will have a dedicated timer node (like all other arch) sooner or later and we will just change TIMER_OF to match that node instead of riscv hart. In this way, we will not do something entirely different from any other architecture. Regards, Atish >> >>> -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); >>> +core_initcall(riscv_timer_init); >> >> Are you sure that core_initcall is not too late? > > No, I'm not at all. This is just intended as a quick throw-away draft. >