From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D2923358AD for ; Wed, 10 Jun 2026 01:49:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781056172; cv=none; b=u+TXbSbED1OUgDdVCNagxKv9vDYhPr8KfbuTLmMc8duvbkOAkPXim/F6iNBJFrdfHv/AxuYSvJDuoVRzr20PZzyuoqiZHZIQZhmsLjtr9qq7N65ouIFtyiG5Z5NckqlVKTDpeM02LuxSwv/zwYzoft1uEsOiVyLABFJAG+pp36I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781056172; c=relaxed/simple; bh=L95PlxhPl6kmTn61tiCBZEx/+SiD3MRJ0+nrbUragP4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=vC2yGSwGvSp2VWLE/+t3sg2iuLqqU7D+YmlHjIQlGlrZQlLtsKAKZqn0jW9TpTIr/ZAL8ugYRB7ROL5ONV8/Zf9ic3KlN9PSmRj9fhzM4OPOBWGFOY+AA3E9odkWMJ/8uhgZ9Z4IuOFLVgHDgpAeLyR16ctokma7FZY6nmgUlcA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dOPM9zqw; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dOPM9zqw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781056169; x=1812592169; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=L95PlxhPl6kmTn61tiCBZEx/+SiD3MRJ0+nrbUragP4=; b=dOPM9zqw76pd0QCVosT+y4dmCRSj01gvrOssQwDadrIDS61T0kMz3gF7 izWAleY/lQtB7wz2GapFbrrHrYCuNUo5M9wSUCYySX5BuQUJDfZ5CUI2+ PoVSP4AN+QbpTW/09KTfwnaPo+xGPkDD8Oq2V0e0ezDCdBllR14/labJx yeRmFnY5YL/+ekC5j5If8RS5NZk/gZz/bwcmpT9A2XDM13lUsGLg4f1qS VUFo298rTlMdDDm1Q+WiM8xA6FWfsTukAUFS5hToOIzpE3wyr1PSVYw21 evA6QIyWvj5AVioESuod8oPmtgfcpW+bCg1UiXDJ2DZQ1XW0HZQuXdGf3 Q==; X-CSE-ConnectionGUID: aDRYPwe+TFqR9lRTTf2cIg== X-CSE-MsgGUID: PmIiqUHpTaGJMSbnAdlchA== X-IronPort-AV: E=McAfee;i="6800,10657,11812"; a="81816813" X-IronPort-AV: E=Sophos;i="6.24,197,1774335600"; d="scan'208";a="81816813" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2026 18:49:28 -0700 X-CSE-ConnectionGUID: PDFZa3bOS3aVba9b3I1KeQ== X-CSE-MsgGUID: 9X5pPC8jSM2dxCBQwPiSXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,197,1774335600"; d="scan'208";a="270033570" Received: from unknown (HELO [10.238.1.211]) ([10.238.1.211]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2026 18:49:24 -0700 Message-ID: Date: Wed, 10 Jun 2026 09:49:10 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/6] Introduce MMIO-based CMT access for Enhanced RDT To: Chen Yu , tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com References: Content-Language: en-US From: "Ning, Hongyu" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/6/2026 10:31 AM, Chen Yu wrote: > Intel Enhanced Resource Director Technology (ERDT) extends the existing > RDT framework with two major capabilities: > > 1. MMIO-based access to monitoring and allocation registers, replacing > the legacy MSR-based interface. > 2. Region-aware RDT for fine-grained control over different tiers of > memory (e.g., CXL.mem, DDR). > > This is described in the Intel RDT Architecture Specification: > https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf > > This patch set focuses on the first part: enabling MMIO-based access for > Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR. > The platform advertises the MMIO register layout through the ACPI ERDT > (Enhanced Resource Director Technology) table, which contains sub-tables > describing per-domain register regions for monitoring and allocation. > > With ERDT, L3 cache occupancy counters are read via MMIO rather than > MSR, allowing the reads to be performed from any CPU without requiring > cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD, > CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads, > and adds initial support for reading L3 occupancy via the CMRC interface. > > kselftest of CMT and L3_CAT has passed with minor adjustment at > https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/. > > Changes from V2 to V3: > - Wrap __resctrl_arch_late_init() to avoid the goto logic. (Thomas Gleixner) > - Make the variables in struct erdt_domain_info tabular format (Thomas Gleixner) > - Remove tail comments (Thomas Gleixner) > - Make the name of erdt_enabled() and variable in it consistent and > comprehensible. (Thomas Gleixner) > - Use topo_lookup_cpuid() to search the CPU id according to the x2apic id > (Thomas Gleixner) > - Fix kernel doc comment format (Thomas Gleixner) > - Use brackets for multiple lines "if" case. (Thomas Gleixner) > - Let the parameter for cacd_init() to fully utilize 100 characters. > (Thomas Gleixner) > - Variables are reordered in reverse fir-tree.(Thomas Gleixner) > - Added a named constant and use it in the rmdd->flags check. > (Thomas Gleixner) > - Introduce helper functions to make the code readable when iterating > the RMDD tables. (Thomas Gleixner) > - Make the macros tabular format. (Thomas Gleixner) > > Changes from V1 to V2: > - Add #include to follow the "include-what-you-use" best > practice (Tony Luck) > - Fix 3 issues reported by: > https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com > Remove the variable of cacd in struct erdt_domain_info as it will > never be used after initialization. > Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and > rdt_mon_capable are both false. > Adjust the comments suggested by sashiko. > > Anil S Keshavamurthy (1): > x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID > > Chen Yu (4): > x86/resctrl: Parse ACPI CMRC table > x86/resctrl: Rename prev_msr to prev_mon_val > x86/resctrl: Refactor the monitor read function > x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO > read > > Tony Luck (1): > fs/resctrl: Do not invoke smp_processor_id() in preemptible context > > arch/x86/Kconfig | 4 +- > arch/x86/include/asm/apic.h | 1 + > arch/x86/include/asm/resctrl.h | 4 + > arch/x86/kernel/cpu/resctrl/Makefile | 1 + > arch/x86/kernel/cpu/resctrl/core.c | 16 +- > arch/x86/kernel/cpu/resctrl/erdt.c | 433 +++++++++++++++++++++++++ > arch/x86/kernel/cpu/resctrl/internal.h | 11 +- > arch/x86/kernel/cpu/resctrl/monitor.c | 64 ++-- > arch/x86/kernel/cpu/topology.c | 2 +- > fs/resctrl/monitor.c | 41 ++- > 10 files changed, 535 insertions(+), 42 deletions(-) > create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c > Tested-by: Hongyu Ning