From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Rob Clark <robdclark@gmail.com>
Cc: Akhil P Oommen <akhilpo@codeaurora.org>,
freedreno@lists.freedesktop.org,
Kristian H Kristensen <hoegsberg@google.com>,
dri-devel@lists.freedesktop.org,
iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCHv10 4/9] iommu/arm-smmu: Move non-strict mode to use io_pgtable_domain_attr
Date: Wed, 25 Nov 2020 12:30:13 +0530 [thread overview]
Message-ID: <c191265f3db1f6b3e136d4057ca917666680a066.1606287059.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1606287059.git.saiprakash.ranjan@codeaurora.org>
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 15 +++++++++------
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 -
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 4b9b10fe50ed..d8979bb71fc0 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -786,9 +786,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
goto out_clear_smmu;
}
- if (smmu_domain->non_strict)
- pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
-
if (smmu_domain->pgtbl_cfg.quirks)
pgtbl_cfg.quirks |= smmu_domain->pgtbl_cfg.quirks;
@@ -1526,9 +1523,12 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
break;
case IOMMU_DOMAIN_DMA:
switch (attr) {
- case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
- *(int *)data = smmu_domain->non_strict;
+ case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: {
+ bool non_strict = smmu_domain->pgtbl_cfg.quirks &
+ IO_PGTABLE_QUIRK_NON_STRICT;
+ *(int *)data = non_strict;
return 0;
+ }
default:
return -ENODEV;
}
@@ -1578,7 +1578,10 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
case IOMMU_DOMAIN_DMA:
switch (attr) {
case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
- smmu_domain->non_strict = *(int *)data;
+ if (*(int *)data)
+ smmu_domain->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
+ else
+ smmu_domain->pgtbl_cfg.quirks &= ~IO_PGTABLE_QUIRK_NON_STRICT;
break;
default:
ret = -ENODEV;
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index bb5a419f240f..cb7ca3a444c9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -368,7 +368,6 @@ struct arm_smmu_domain {
const struct iommu_flush_ops *flush_ops;
struct arm_smmu_cfg cfg;
enum arm_smmu_domain_stage stage;
- bool non_strict;
struct mutex init_mutex; /* Protects smmu pointer */
spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */
struct iommu_domain domain;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-11-25 7:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 7:00 [PATCHv10 0/9] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 1/9] iommu/io-pgtable: Add a domain attribute for pagetable configuration Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 2/9] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 3/9] iommu/arm-smmu: Add support for pagetable config domain attribute Sai Prakash Ranjan
2020-11-25 7:00 ` Sai Prakash Ranjan [this message]
2020-11-25 7:00 ` [PATCHv10 5/9] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 6/9] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 7/9] drm/msm/a6xx: Add support for using system cache on MMU500 based targets Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 8/9] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 9/9] iommu: arm-smmu-impl: Add a space before open parenthesis Sai Prakash Ranjan
2020-11-25 14:05 ` [PATCHv10 0/9] System Cache support for GPU and required SMMU support Will Deacon
2020-11-25 14:05 ` Will Deacon
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