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Thu, 12 Dec 2024 05:31:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BC5V804029685 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 05:31:08 GMT Received: from hu-pkondeti-hyd (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 21:31:03 -0800 Date: Thu, 12 Dec 2024 11:01:00 +0530 From: Pavan Kondeti To: Marc Zyngier CC: Pavan Kondeti , Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Elliot Berman , , , , , Subject: Re: [PATCH] drm/msm/a6xx: Skip gpu secure fw load in EL2 mode Message-ID: References: <20241209-drm-msm-kvm-support-v1-1-1c983a8a8087@quicinc.com> <87ed2fs03w.wl-maz@kernel.org> <92cee905-a505-4ce9-9bbc-6fba4cea1d80@quicinc.com> <86sequsdtp.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <86sequsdtp.wl-maz@kernel.org> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tyQb_xK72c8u2XdN2OgQP_4VMJmSutu8 X-Proofpoint-GUID: tyQb_xK72c8u2XdN2OgQP_4VMJmSutu8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 mlxlogscore=968 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120037 On Wed, Dec 11, 2024 at 10:40:02AM +0000, Marc Zyngier wrote: > On Wed, 11 Dec 2024 00:37:34 +0000, > Pavan Kondeti wrote: > > > > On Tue, Dec 10, 2024 at 09:24:03PM +0000, Marc Zyngier wrote: > > > > +static int a6xx_switch_secure_mode(struct msm_gpu *gpu) > > > > +{ > > > > + int ret; > > > > + > > > > +#ifdef CONFIG_ARM64 > > > > + /* > > > > + * We can access SECVID_TRUST_CNTL register when kernel is booted in EL2 mode. So, use it > > > > + * to switch the secure mode to avoid the dependency on zap shader. > > > > + */ > > > > + if (is_kernel_in_hyp_mode()) > > > > + goto direct_switch; > > > > > > No, please. To check whether you are *booted* at EL2, you need to > > > check for is_hyp_available(). Whether the kernel runs at EL1 or EL2 is > > > none of the driver's business, really. This is still absolutely > > > disgusting from an abstraction perspective, but I guess we don't have > > > much choice here. > > > > > > > Thanks Marc. Any suggestions on how we can make is_hyp_mode_available() > > available for modules? Do you prefer exporting > > kvm_protected_mode_initialized and __boot_cpu_mode symbols directly or > > try something like [1]? > > Ideally, neither. These were bad ideas nine years ago, and they still > are. The least ugly hack I can come up with is the patch below, and > you'd write something like: > > if (cpus_have_cap(ARM64_HAS_EL2_OWNERSHIP)) > blah(); > > This is obviously completely untested. > I have tested your patch. It works as intended. Thanks Marc. > It also doesn't solve the problem of the kernel booted on bare-metal > at EL1, or with a hypervisor that doesn't change the programming > interface of the device under the guest's feet. Eventually, someone > will have to address these cases. > Noted, Thanks. ~Pavan