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Mon, 28 Apr 2025 10:41:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHgjfMkBn0pV9r4Qg3qhNII5Usb8joBTmFadTYCHZoBgt9OiIPYvsOPn9WNpttYgRk3jvRtAA== X-Received: by 2002:a05:6a00:88f:b0:736:3c6a:be02 with SMTP id d2e1a72fcca58-73fd75c4ea4mr15399426b3a.11.1745862070246; Mon, 28 Apr 2025 10:41:10 -0700 (PDT) Received: from [192.168.0.195] ([49.204.26.142]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25942157sm8304691b3a.72.2025.04.28.10.41.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 10:41:10 -0700 (PDT) Message-ID: Date: Mon, 28 Apr 2025 23:11:05 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs To: Luca Weiss , Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , AngeloGioacchino Del Regno Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250425-sm6350-gdsc-val-v1-0-1f252d9c5e4e@fairphone.com> <20250425-sm6350-gdsc-val-v1-4-1f252d9c5e4e@fairphone.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20250425-sm6350-gdsc-val-v1-4-1f252d9c5e4e@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=ZpvtK87G c=1 sm=1 tr=0 ts=680fbdb7 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Svr01UFivMFfsnZ9dZkWgg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=6H0WHjuAAAAA:8 a=COk6AnOGAAAA:8 a=6dQnf3u2Ryt8jKbU0REA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=Soq9LBFxuPC4vsCAQt-j:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: A3zeYHdeIabkiZ_t4NXoqGwnFBrIxQAo X-Proofpoint-GUID: A3zeYHdeIabkiZ_t4NXoqGwnFBrIxQAo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDE0MyBTYWx0ZWRfX9AJxJxy7zcK4 Rsx8yjXbpk1YlcljtfM8HbIO40e6uUbA+LFqZwoaGZl1E8A7uWbnVKcRZqDAMyZLQPkZPbZNOwZ jO198uyxI6Yl1RZ/HiD1svEljQQCnhD0/nSLFw2/8T7dfMwY6IYy3Xc0PeiX45lmtJQ9PcETF1q YQzMgPdkICJuiVUUv9Kc4INdNwT2rU5Y4OuXHaYigBxS8VfxQqecHmBt7i9dPIDHg9Sv5FapkrW 8GutNdkpwZtCcO+c0D41paP5AntQULyFC3LZt+99y1tqjJTHvpQoPQVSJc1QhVoepoiJkiDSwxD bnTJUPV2FgmRomuYWYEA8QwExbGAZ/MUQX6pJ0SUcyGAxdkSELROZmp5XmHHT/jMuHAuUewMKfw VgRfF2CHAiwmFQi3muAgqO28/qezpAbBP1EHRYE8HWYhGeaFQh3Tmo5DqiqiMkmdTg07Prnb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 adultscore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280143 On 4/25/2025 5:42 PM, Luca Weiss wrote: > Compared to the msm-4.19 driver the mainline GDSC driver always sets the > bits for en_rest, en_few & clk_dis, and if those values are not set > per-GDSC in the respective driver then the default value from the GDSC > driver is used. The downstream driver only conditionally sets > clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. > > Correct this situation by explicitly setting those values. For all GDSCs > the reset value of those bits are used, with the exception of > gpu_cx_gdsc which has an explicit value (qcom,clk-dis-wait-val = <8>). > > Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") > Signed-off-by: Luca Weiss > --- > drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c > index 35ed0500bc59319f9659aef81031b34d29fc06a4..ee89c42413f885f21f1470b1f7887d052e52a75e 100644 > --- a/drivers/clk/qcom/gpucc-sm6350.c > +++ b/drivers/clk/qcom/gpucc-sm6350.c > @@ -413,6 +413,9 @@ static struct clk_branch gpu_cc_gx_vsense_clk = { > static struct gdsc gpu_cx_gdsc = { > .gdscr = 0x106c, > .gds_hw_ctrl = 0x1540, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x8, > .pd = { > .name = "gpu_cx_gdsc", > }, > @@ -423,6 +426,9 @@ static struct gdsc gpu_cx_gdsc = { > static struct gdsc gpu_gx_gdsc = { > .gdscr = 0x100c, > .clamp_io_ctrl = 0x1508, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x2, > .pd = { > .name = "gpu_gx_gdsc", > .power_on = gdsc_gx_do_nothing_enable, > Reviewed-by: Taniya Das