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Even with a timeout you want both to be signalling >>> path. >>> >>> I guess more generally, if a fence is signalled by mechanism A or B, >>> whichever happens first, you have the choice between: >> >> That doesn't happen in practice. >> >> For each fence you only have one signaling path you need to guarantee forward progress for. >> >> All other signaling paths are just opportunistically optimizations which *can* signal the fence, but there is no guarantee that they will. > > Are you now referring to the fast-path callbacks like fence->ops- >> is_signaled()? Or are you talking about different reference holders > which might want to signal? Yes, I'm referring to the is_signaled() callback. When you have multiple reference holders which can all signal the fence by calling dma_fence_signal then there is clearly something going wrong. What can be is that you have something like a fallback timer for buddy HW which swallows IRQs (e.g. like radeon or amdgpu have), but then you have something like a high level spinlock which makes sure that your IRQ handler is neither re-entrant nor multiple instances running at the same time on different CPUs. >> >> We used to have some exceptions to that, especially around aborting submissions, but those turned out to be a really bad idea as well.  >> >> Thinking more about it you should probably enforce that there is only one signaling path for each fence signaling. > > An idea that is floating around is to move the entire fence signaling > functionality into the dma fence context. That would have exclusive > access, and could also finally guarantee that fences must be signaled > in order. That sounds like a sane idea to me. Regards, Christian. > > > P.