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Tue, 23 May 2023 04:40:50 -0700 (PDT) Message-ID: Date: Tue, 23 May 2023 19:40:45 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 3/5] arm64/sysreg: Convert MDSCR_EL1 to automatic register generation Content-Language: en-US To: Mark Brown , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev References: <20230419-arm64-syreg-gen-v1-0-936cd769cb9e@kernel.org> <20230419-arm64-syreg-gen-v1-3-936cd769cb9e@kernel.org> From: Shaoqin Huang In-Reply-To: <20230419-arm64-syreg-gen-v1-3-936cd769cb9e@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/23/23 00:22, Mark Brown wrote: > Convert MDSCR_EL1 to automatic register generation as per DDI0616 2023-03. > No functional change. > Reviewed-by: Shaoqin Huang > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 1 - > arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ > 2 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 4e48bb4dca6a..4ecae92b56b5 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -134,7 +134,6 @@ > #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) > #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) > > -#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) > #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) > #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) > #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 1699e87bc0b4..a5ae0e19fc9f 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -55,6 +55,34 @@ Field 29 TX > Res0 28:0 > EndSysreg > > +Sysreg MDSCR_EL1 2 0 0 2 2 > +Res0 63:36 > +Field 35 EHBWE > +Field 34 EnSPM > +Field 33 TTA > +Field 32 EMBWE > +Field 31 TFO > +Field 30 RXfull > +Field 29 TXfull > +Res0 28 > +Field 27 RXO > +Field 26 TXU > +Res0 25:24 > +Field 23:22 INTdis > +Field 21 TDA > +Res0 20 > +Field 19 SC2 > +Res0 18:16 > +Field 15 MDE > +Field 14 HDE > +Field 13 KDE > +Field 12 TDCC > +Res0 11:7 > +Field 6 ERR > +Res0 5:1 > +Field 0 SS > +EndSysreg > + > Sysreg ID_PFR0_EL1 3 0 0 1 0 > Res0 63:32 > UnsignedEnum 31:28 RAS > -- Shaoqin