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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac7c018aeadsm144626866b.153.2025.04.03.13.52.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Apr 2025 13:52:31 -0700 (PDT) Message-ID: Date: Thu, 3 Apr 2025 22:52:28 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 4/4] PCI: dwc: Add support for configuring lane equalization presets To: Manivannan Sadhasivam , Konrad Dybcio Cc: Krishna Chaitanya Chundru , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> <20250316-preset_v6-v8-4-0703a78cb355@oss.qualcomm.com> <3sbflmznjfqpcja52v6bso74vhouv7ncuikrba5zlb74tqqb5u@ovndmib3kgqf> <92c4854d-033e-c7b5-ca92-cf44a1a8c0cc@oss.qualcomm.com> <5fece4ac-2899-4e7d-8205-3b1ebba4b56b@oss.qualcomm.com> <622788fa-a067-49ac-b5b1-e4ec339e026f@oss.qualcomm.com> <4rep2gvymazkk7pgve36cw7moppozaju7h6aqc3gflxrvkskig@62ykri6v4trs> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=AMoviu7M c=1 sm=1 tr=0 ts=67eef511 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=8zO8dPC1Pt-TAjq7ZcgA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: _6qIIXdntGggQpLeRf08UmNny-nIpAsL X-Proofpoint-ORIG-GUID: _6qIIXdntGggQpLeRf08UmNny-nIpAsL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-03_09,2025-04-03_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 impostorscore=0 clxscore=1015 spamscore=0 phishscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504030110 On 4/2/25 8:02 AM, Manivannan Sadhasivam wrote: > On Sat, Mar 29, 2025 at 12:42:02PM +0100, Konrad Dybcio wrote: >> On 3/29/25 10:39 AM, Manivannan Sadhasivam wrote: >>> On Sat, Mar 29, 2025 at 09:59:46AM +0100, Konrad Dybcio wrote: >>>> On 3/29/25 7:30 AM, Manivannan Sadhasivam wrote: >>>>> On Fri, Mar 28, 2025 at 10:53:19PM +0100, Konrad Dybcio wrote: >>>>>> On 3/28/25 7:45 AM, Manivannan Sadhasivam wrote: >>>>>>> On Fri, Mar 28, 2025 at 11:04:11AM +0530, Krishna Chaitanya Chundru wrote: [...] >> Ohh, I didn't think about that - and I can only think about solutions that are >> rather janky.. with perhaps the least janky one being changing the else case I >> proposed above into: >> >> else if (speed >= PCIE_SPEED_32_0GT && eq_presets_Ngts[speed - PCIE_SPEED_16_0GT][0] != PCI_EQ_RESV) { > > s/PCIE_SPEED_16_0GT/PCIE_SPEED_32_0GT > >> ... > > So this I read as: Oh, your controller supports 32 GT/s and you firmware also > wanted to apply the custom preset offsets, but sorry we didn't do it because we > don't know if it would work or not. So please let us know so that we can work > with you test it and then finally we can apply the presets. Good, because that was exactly what I had in mind :) >>>>> I'm not forseeing any issue in this part of the code to support higher GEN >>>>> speeds though. >>>> >>>> I would hope so as well, but both not programming and misprogramming are >>>> equally hard to detect >>>> >>> >>> I don't disagree. I wanted to have it since there is no sensible way of warning >>> users that this part of the code needs to be updated in the future. >> >> I understand, however I'm worried that the programming sequence or register >> may change for higher speeds in a way that would be incompatible with what >> we assume here >> > > Honestly, I don't know why you are having this opinion. This piece of code is > not in Qcom driver and the registers are the same for 8 GT/s, 16 GT/s as per the > PCIe spec. So the hardware programming sequence and other arguments doesn't > apply here (atleast to me). I'm not familiar with the spec, but if you think it's a good idea to extend the sequence for 32+ GT/s, I won't object anymore Konrad