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Fri, 04 Oct 2024 17:50:33 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494HoW2Y019311 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 17:50:32 GMT Received: from [10.226.59.182] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 10:50:31 -0700 Message-ID: Date: Fri, 4 Oct 2024 11:50:30 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH V3 05/11] accel/amdxdna: Add hardware context Content-Language: en-US To: Lizhi Hou , , CC: , , , , References: <20240911180604.1834434-1-lizhi.hou@amd.com> <20240911180604.1834434-6-lizhi.hou@amd.com> From: Jeffrey Hugo In-Reply-To: <20240911180604.1834434-6-lizhi.hou@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: X-JDjG1V8kxyHiMPqmbi2sb6y3IiSBTn X-Proofpoint-ORIG-GUID: X-JDjG1V8kxyHiMPqmbi2sb6y3IiSBTn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040123 On 9/11/2024 12:05 PM, Lizhi Hou wrote: > diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c > new file mode 100644 > index 000000000000..52a71661f887 > --- /dev/null > +++ b/drivers/accel/amdxdna/aie2_ctx.c > @@ -0,0 +1,186 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024, Advanced Micro Devices, Inc. > + */ > + > +#include > +#include > +#include > +#include > + > +#include "amdxdna_ctx.h" > +#include "amdxdna_mailbox.h" > +#include "amdxdna_pci_drv.h" > +#include "aie2_pci.h" > +#include "aie2_solver.h" Alphabetical order? > +/** > + * struct amdxdna_drm_create_hwctx - Create hardware context. > + * @ext: MBZ. > + * @ext_flags: MBZ. > + * @qos_p: Address of QoS info. > + * @umq_bo: BO handle for user mode queue(UMQ). > + * @log_buf_bo: BO handle for log buffer. > + * @max_opc: Maximum operations per cycle. > + * @num_tiles: Number of AIE tiles. > + * @mem_size: Size of AIE tile memory. > + * @umq_doorbell: Returned offset of doorbell associated with UMQ. > + * @handle: Returned hardware context handle. > + * @pad: MBZ. You specify must be zero, but I don't see that checked anywhere. > + */ > +struct amdxdna_drm_create_hwctx { > + __u64 ext; > + __u64 ext_flags; > + __u64 qos_p; > + __u32 umq_bo; > + __u32 log_buf_bo; > + __u32 max_opc; > + __u32 num_tiles; > + __u32 mem_size; > + __u32 umq_doorbell; > + __u32 handle; > + __u32 pad; > +};