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[79.129.51.141]) by smtp.gmail.com with ESMTPSA id 92sm24201125wra.19.2020.09.14.13.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 13:28:12 -0700 (PDT) From: Cristian Ciocaltea To: Marc Zyngier , Rob Herring , Manivannan Sadhasivam , Thomas Gleixner , Jason Cooper , =?UTF-8?q?Andreas=20F=C3=A4rber?= Cc: parthiban@linumiz.com, Saravanan Sekar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org Subject: [PATCH v7 1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding Date: Mon, 14 Sep 2020 23:27:17 +0300 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700 and S900 SoCs and provides support for handling up to 3 external interrupt lines. Signed-off-by: Cristian Ciocaltea --- Changes in v7: - None Changes in v6: - Got rid of the 'actions,owl-sirq' compatible, per Robs's feedback - Replaced 'actions,ext-interrupts' with 'interrupts', as agreed with Rob and Marc Changes in v5: - Updated controller description statements both in the commit message and the binding doc .../actions,owl-sirq.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml new file mode 100644 index 000000000000..5da333c644c9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi Owl SoCs SIRQ interrupt controller + +maintainers: + - Manivannan Sadhasivam + - Cristian Ciocaltea + +description: | + This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700 + and S900) and provides support for handling up to 3 external interrupt lines. + +properties: + compatible: + enum: + - actions,s500-sirq + - actions,s700-sirq + - actions,s900-sirq + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the input IRQ number, between 0 and 2, while the second + cell is the trigger type as defined in interrupt.txt in this directory. + + 'interrupts': + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. + They shall be specified sequentially from output 0 to 2. + minItems: 3 + maxItems: 3 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - 'interrupts' + +additionalProperties: false + +examples: + - | + #include + + sirq: interrupt-controller@b01b0200 { + compatible = "actions,s500-sirq"; + reg = <0xb01b0200 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* SIRQ0 */ + , /* SIRQ1 */ + ; /* SIRQ2 */ + }; + +... -- 2.28.0