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Sun, 06 Jul 2025 07:22:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFO93oCbUuKR455AbSvqBvRYCReXzTUnYblW52a/kTh3+cnV2a1b0uxIXTMZ96Ppo2+XoCvjw== X-Received: by 2002:a17:902:c943:b0:221:751f:cfbe with SMTP id d9443c01a7336-23c8595204cmr167336735ad.19.1751811719650; Sun, 06 Jul 2025 07:21:59 -0700 (PDT) Received: from [192.168.1.5] ([106.222.234.15]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c8431a4c6sm63428015ad.46.2025.07.06.07.21.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Jul 2025 07:21:59 -0700 (PDT) Message-ID: Date: Sun, 6 Jul 2025 19:51:55 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iommu/arm-smmu: disable PRR on SM8250 To: Dmitry Baryshkov , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bibek Kumar Patro Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Akhil P Oommen References: <20250705-iommu-fix-prr-v2-1-406fecc37cf8@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20250705-iommu-fix-prr-v2-1-406fecc37cf8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=FrUF/3rq c=1 sm=1 tr=0 ts=686a8689 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=D9rl3thw99EfY5kE3N+1UQ==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=idnX5w4AHIxaUxQtNqEA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA2MDA5MSBTYWx0ZWRfX45JfCggvF6O1 gixpB57BHVYePO/as8pJDQrBTBctD0MPIUS+s7rodVjiBqwUiMqoGG/8GtbXwhHs6L4BZ7FnaI5 WKMm2z0tCyDNACm2eKipvlFdbmzDSvoRlLYL5zpvH3YwFtNdWH9PrLO96kd0IPBDwA0XLBnxM3v 2plkJ4mOnAieO9OyuaVtJ01IyAoL5FjKgHCrKUFMqAOLVxmQARG30m3g2pqz8c63hDiDVHxSIB8 oFo/cXmRLeuFfTayr3MDqHnrFiq/Bw4F165abVUFuI9N0ZWe56r6owsdOSeGFYs0NRYT7OfsPEI YRq6VqRm5ENKbSH1mBXZSQoa0xkeZKDG7ptW0JDS1QY3yIvhfYVs9WmvXiDxwOAtObD699LuIu8 1ZA6Q7gjobp6aYuvCr7+xOuedp9+JxwGPkPz7P6sRGfjcG8QyHYJTY2g0blqP0kDWhql1sJh X-Proofpoint-GUID: BLTkZtTYJ7NFTPEGSe_vcC65Mk0BaOtJ X-Proofpoint-ORIG-GUID: BLTkZtTYJ7NFTPEGSe_vcC65Mk0BaOtJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-04_07,2025-07-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 clxscore=1015 mlxscore=0 spamscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507060091 On 7/5/2025 9:38 PM, Dmitry Baryshkov wrote: > On SM8250 / QRB5165-RB5 using PRR bits resets the device, most likely > because of the hyp limitations. Disable PRR support on that platform. > > Fixes: 7f2ef1bfc758 ("iommu/arm-smmu: Add support for PRR bit setup") > Signed-off-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Unfortunately, there is no way to detect firmware support for PRR safely from KMD. -Akhil. > --- > I currently don't have access to other devices from these generations. > It might be necessary to apply the same workaround to other platforms. > --- > Changes in v2: > - Simplify the workaround as the issue seems to be limited to SM8250 > only (Rob) > - Link to v1: https://lore.kernel.org/r/20250705-iommu-fix-prr-v1-1-ef725033651c@oss.qualcomm.com > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 62874b18f6459ad9a8b0542ab81c24e3e745c53d..53d88646476e9f193a6275d9c3ee3d084c215362 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -355,7 +355,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > priv->set_prr_addr = NULL; > > if (of_device_is_compatible(np, "qcom,smmu-500") && > - of_device_is_compatible(np, "qcom,adreno-smmu")) { > + !of_device_is_compatible(np, "qcom,sm8250-smmu-500") && > + of_device_is_compatible(np, "qcom,adreno-smmu")) { > priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit; > priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr; > } > > --- > base-commit: 7244e36657076b597ac21d118be9c0b0f15fc622 > change-id: 20250705-iommu-fix-prr-600451b1d304 > > Best regards,