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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f2e2ffac2sm59877271c88.11.2025.12.16.16.46.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Dec 2025 16:46:58 -0800 (PST) Message-ID: Date: Tue, 16 Dec 2025 16:46:56 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali To: Vladimir Zapolskiy , Konrad Dybcio , Bryan O'Donoghue , Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Mauro Carvalho Chehab Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251113-add-support-for-camss-on-kaanapali-v6-0-1e6038785a8e@oss.qualcomm.com> <20251113-add-support-for-camss-on-kaanapali-v6-1-1e6038785a8e@oss.qualcomm.com> <37d0f89f-69be-45a7-90fa-347d6a3800bf@oss.qualcomm.com> <2d7ac7e8-ab69-44a6-b732-3657abf3a5a6@oss.qualcomm.com> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: CwAg7ocvwvpjKulQZ4ZM08tsTF7X5i7o X-Authority-Analysis: v=2.4 cv=CYoFJbrl c=1 sm=1 tr=0 ts=6941fd83 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yeKN4i86vKkShX6YYCoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE3MDAwMyBTYWx0ZWRfX9A+diKh1bKsv 0SMe/EDnvF1YXyOkxpLg9OFT5e3UIU1GqvNzSPgAg1nsD5Vtv1eqDvm4Npx1oGaDz/hQviASFt3 hd4lEWXKTUEsZmXzTNjEgTwICtkFK28/LddVeUtc520b+9V3qdD0Xj2PjgbcP6y7IJUqddfS7Fd C5iM6BW+4TgMuW66gqtaNCPtpH9gIoaEXlKJYM5oYXuwn+qlSHGsBUHPQW74xx5bRFYH6zedLS9 zPRjj8ySUIpY0NPVMEeqBh5VS8Oa7OLONDrqJANfnObwzqOPJTQHktAvJ+Kg3ctI3A/mp3Q4lHB YD5gRFG89gEhq8JuZ1g9h5I5XbWkyg7kLkvYkPlawTxen8QUJYA7kZ/jqKbxJveNy9uiKBvQJLb 8OXdCJtBnI4jWIaPZzPCCys2ttL/6w== X-Proofpoint-ORIG-GUID: CwAg7ocvwvpjKulQZ4ZM08tsTF7X5i7o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-16_03,2025-12-16_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170003 On 12/16/2025 4:02 PM, Vladimir Zapolskiy wrote: > Hi Vijay. > > On 12/16/25 19:55, Vijay Kumar Tumati wrote: >> >> On 12/12/2025 4:49 AM, Vladimir Zapolskiy wrote: >>> On 11/18/25 20:44, Konrad Dybcio wrote: >>>> On 11/18/25 7:25 PM, Vijay Kumar Tumati wrote: >>>>> >>>>> On 11/18/2025 7:00 AM, Bryan O'Donoghue wrote: >>>>>> On 14/11/2025 03:29, Hangxiang Ma wrote: >>>>>>> +                  <0x0 0x0900e000 0x0 0x1000>, >>>>>> >>>>>> Why aren't you starting @ 0x0900e000 ? seems to be omitting some of >>>>>> the registers in the ICP block. Should start at +0xd000 not >>>>>> +0xe000 ? >>>>>> >>>>>>> +                  <0x0 0x0902e000 0x0 0x1000>, >>>>>> >>>>>> Same here. >>>>> Hi Bryan, HLOS does not have access to those registers. They are >>>>> configured by the Hyp. >>>> >>>> If that's hyp, please add them. We already have platforms without >>>> Gunyah. Remember, bindings are defined once and for good and I >>>> wouldn't >>>> call it impossible that someone would want to run that >>>> configuration on >>>> Kaanapali some day >>>> >>> >>> If the ICP register block is added now, then it will practically >>> exclude >>> an option to run hardware demosaic on Kaanapali. There were notorious >>> and still unresolved problems with CSIPHY blocks, which shall be split >>> from CSID/VFE CAMSS on device tree level also, for similar reasons the >>> same should be done with ICP or other blocks. It makes exactly zero >>> sense to pile everything into a monolythic device tree node, and doing >>> so undermines any future advances in CAMSS support in the upstream >>> Linux, the hardware description in downstream is done thoughtfully >>> better, >>> and not for no reason. >>> >> Hi Vladimir, yes, this has been discussed in the past and the general >> consensus from everyone is for not blocking KNP series on this. But yes, >> there is an ongoing effort to modularize the bindings for future >> chipsets and when it's ready, we can review, discuss and take it > > My concern is that it makes very little sense to throw any not clearly > defined hardware properties and interconnections into an unorganized and > unmanageable pile of everything, because this closes the door to ever > update > the upstream CAMSS driver by adding better CAMSS IP support for any > already > manufactured and sold Qualcomm SoC powered board with done CAMSS support. > > If some user already holds a phone, a laptop and expects to offload > CPU to > CAMSS IP one happy day, it's pretty unsatisfactory to say that it will > never > happen on legacy hardware, because there was done an unrecoverable > mistake > by adding never tested properties into CAMSS DT bindings, and the > remained > option is to "wait for future chipsets". Each added unsupported and > unused > property boards up the window of better CAMSS support on manufactured > boards. > > I don't understand a reason why to do worse for the upstream, when > there is > a clear and feasible alternative not to do worse, thus my > misunderstanding > and my grief for upstream CAMSS are my concerns. > Thanks for the comments, Vladimir. Bryan's and Krzysztof's argument was that the bindings are required to describe the full hardware regardless of the driver support and either way not modifiable in the future, so they preferred having the HW properties of the key functional blocks in the bindings. And we were specifically asked to add the properties into this node in this patch series. Having said that, my knowledge on how the bindings are handled upstream in the long run as the requirements evolve, is limited. So I will look for some expert advise from Bryan here as he strongly advised for these. Thanks again. >> forward. As for your ICP concern, if you are referring to the Demosaic >> in OFE, I believe we might still be able to do it either with direct OFE >> config from CPU or using the firmware (preferred), given that we >> properly establish the shared memory and SID IOVA ranges for ICP, >> assuming that the load and authenticate will be taken care by Hyp or TZ. >> Please share your thoughts if I missed something. >> >> Hi Bryan, please feel free to add your thoughts. >> >