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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3bbe6c5660sm2390825a12.48.2025.07.10.07.29.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jul 2025 07:29:53 -0700 (PDT) Message-ID: Date: Thu, 10 Jul 2025 16:29:46 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4] selftests: riscv: add misaligned access testing To: Andreas Schwab Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Shuah Khan , Alexandre Ghiti References: <20250710133506.994476-1-cleger@rivosinc.com> <5db9ec69-d0e4-4113-a989-ac75d0f1e5dd@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 10/07/2025 16:23, Andreas Schwab wrote: > On Jul 10 2025, Clément Léger wrote: > >> On 10/07/2025 15:53, Andreas Schwab wrote: >>> On Jul 10 2025, Clément Léger wrote: >>> >>>> This selftest tests all the currently emulated instructions (except for >>>> the RV32 compressed ones which are left as a future exercise for a RV32 >>>> user). For the FPU instructions, all the FPU registers are tested. >>> >>> If that didn't catch the missing sign extension that I just fixed in >>> , you >>> should consider extending the tests. >>> >> >> Hi Andreas, you link doesn't work and I didn't find anything about sign >> extension except a patch you wrote for arch_cmpxg(). > > lore.k.o is currently down, here's the patch I have sent: > > From 77c8255da24ee4fac54e2371594d7210d1ddee19 Mon Sep 17 00:00:00 2001 > From: Andreas Schwab > Date: Thu, 10 Jul 2025 13:52:35 +0200 > Subject: [PATCH] riscv: traps_misaligned: properly sign extend value in > misaligned load handler > > Add missing cast to signed long. > > Signed-off-by: Andreas Schwab > --- > arch/riscv/kernel/traps_misaligned.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index 93043924fe6c..f760e4fcc052 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) > } > > if (!fp) > - SET_RD(insn, regs, val.data_ulong << shift >> shift); > + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); Hi Andreas, Nice catch, it seems like it was fixed in OpenSBI but never backported in the kernel. As you suggested, I'll modify the test to test the sign extension. Thanks, Clément > else if (len == 8) > set_f64_rd(insn, regs, val.data_u64); > else