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Sun, 13 Sep 2026 07:43:33 -0700 (PDT) X-Received: by 2002:a17:90b:586f:b0:39b:66ee:a14 with SMTP id 98e67ed59e1d1-39d9c374d49mr21935918a91.25.1789310613011; Sun, 13 Sep 2026 07:43:33 -0700 (PDT) Received: from localhost ([2a12:a305:4::30fb]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d99531b16sm16780590a91.14.2026.09.13.07.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Sep 2026 07:43:32 -0700 (PDT) Date: Sun, 13 Sep 2026 10:43:28 -0400 Message-ID: From: Guodong Xu To: Jonathan Corbet , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Chen Wang , Inochi Amaoto Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, spacemit@lists.linux.dev, sophgo@lists.linux.dev, linux-kselftest@vger.kernel.org, Andrew Jones Subject: Re: [PATCH v6 11/11] riscv: hwprobe: Introduce rva23u64 base behavior In-Reply-To: <20260812-rva23u64-hwprobe-v2-v6-11-c985af3256b8@oss.qualcomm.com> References: <20260812-rva23u64-hwprobe-v2-v6-0-c985af3256b8@oss.qualcomm.com> <20260812-rva23u64-hwprobe-v2-v6-11-c985af3256b8@oss.qualcomm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=e+mT2qp/ c=1 sm=1 tr=0 ts=6aa6b69b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=0YUHzDklBslsgzCo5oAA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEzMDIxMCBTYWx0ZWRfX/+ZYzVNY5HHn CPi5oyic6NOcwBGJC4J8dMDQdfWjWZp3qjp942TvdQjVNoy2dCqsY6oCZM3yHzg9+7SGvRo3X08 K/wasR0rzbR4mM0fQ+rGVQ0TmuZXHXE= X-Proofpoint-ORIG-GUID: XAI9B8wS7zgJzWZIu1AXiK5tIiTRhfcE X-Proofpoint-GUID: XAI9B8wS7zgJzWZIu1AXiK5tIiTRhfcE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEzMDIxMCBTYWx0ZWRfX3d2OrxFDWLUS O+fGqafdpDIbfIUjsFUxg9EsXvy99VWqNAOOL/QBD5hjC0U52gfeLO43eR9V1qYpQNJSc7Z8U3A qjOxXMk7fHT8fvlDgkNuvG1pQgl8sM0ZcOL/SgpC1QJjl9qC0Jt5FFd/TIErJoD1gYd2tJyTMqr fnTrfvbFu5I7bbvvx/JfgY3cyVQOwRej8yQMEme565aDknS+cTyY6mZcm5gvgWJeh7wlJ9OPGRl HdmC9l9wC8/wS2dFcMCcbykEeR3tdHk63dvYQ/9lVMKAfVmftP63xaOvMdXjvuJMWB4dq5vDYgS kzGJCwh+lj2KPWyGatvOzkdWDi/JtFi0umwAEJ+zF5k53hfRX9Xw6pQp/1+f/1zsBWxJAxIUlys iACumHkvCp7qEcRWPrJ5zizA0AVOKGA+fwYQqX3PRuz2ee2RMD2qHL5VQ4Cfztj3Qw2C2LN+8nA UiEuWRUxhn/YdKNieZQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-13_05,2026-09-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609130210 On Wed, 12 Aug 2026 19:33:57 -0400, Guodong Xu wrote: > [...] > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 656cb100ac48..a18465e734b5 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > > [...] > > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > - pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > + pair->value = 0; Today while testing this series with glibc's glibc IFUNC resolver on QEMU (-cpu rva23s64), I found that this hunk introduces an initialization ordering bug, which affects the KEY_BASE_BEHAVIOR valude in vDSO. > + if (hwprobe_has_isa_base(cpus, RISCV_ISA_BASE_IMA)) > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_IMA; > + if (hwprobe_has_isa_base(cpus, RISCV_ISA_BASE_RVA23U64)) > + pair->value |= RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64; > break; Both bits are now derived from hart_isa[cpu].isa_bases, which patch v6 09/11 populates in riscv_init_isa_bases() at subsys_initcall. The vDSO snapshot of all hwprobe values, init_hwprobe_vdso_data(), runs at arch_initcall_sync, which is earlier. So the vDSO copy of RISCV_HWPROBE_KEY_BASE_BEHAVIOR is taken from empty bitmaps and reads 0: raw syscall : key=3 value=0x3 (IMA | RVA23U64) __riscv_hwprobe (vDSO) : key=3 value=0x0 Mainline returns 0x1 on both paths, so this also regresses the IMA bit for every vDSO user of key 3. The selftests did not catch it because they call the system call directly (sys_hwprobe.S); glibc's __riscv_hwprobe() takes the vDSO fast path and did. The fix is to register riscv_init_isa_bases() at arch_initcall instead of subsys_initcall. That is still after core_initcall(tagged_addr_init), which it depends on, and before arch_initcall_sync. It belongs in patch 09/11 and I will fold it in there in v7. With it both paths return 0x3, and the hwprobe, cbo and which-cpus selftests pass on rva23s64, rva22s64 and on mainline. I will send v7. Thanks for your patience. BR, Guodong